diff options
author | Eric Anholt <[email protected]> | 2011-05-10 12:55:12 -0700 |
---|---|---|
committer | Eric Anholt <[email protected]> | 2011-05-18 13:57:17 -0700 |
commit | 136eb2bde769713b100351ff96bceb970f068c0a (patch) | |
tree | 539b829ece242593f809dd4a4b196faf21eed52c /src/mesa/drivers/dri | |
parent | 27b03926618ddcafabb7b61e652fe6458b017b24 (diff) |
i965/fs: Add support for "if" statements in 16-wide mode on gen6+.
It turns out there's nothing in the hardware preventing this. It
appears that it ought to work on pre-gen6 as well, but just produces
GPU hangs.
Improves glbenchmark Egypt framerate 4.4% +/- 0.3% (n=3), and Pro by
2.6% +/- 0.6% (n=3).
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 007f58c341c..2d41302d15a 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1003,7 +1003,11 @@ gen6_IF(struct brw_compile *p, uint32_t conditional, insn = next_insn(p, BRW_OPCODE_IF); brw_set_dest(p, insn, brw_imm_w(0)); - insn->header.execution_size = BRW_EXECUTE_8; + if (p->compressed) { + insn->header.execution_size = BRW_EXECUTE_16; + } else { + insn->header.execution_size = BRW_EXECUTE_8; + } insn->bits1.branch_gen6.jump_count = 0; brw_set_src0(p, insn, src0); brw_set_src1(p, insn, src1); diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 018a16e4322..5232a7f77af 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1859,7 +1859,7 @@ fs_visitor::visit(ir_if *ir) { fs_inst *inst; - if (c->dispatch_width == 16) { + if (intel->gen != 6 && c->dispatch_width == 16) { fail("Can't support (non-uniform) control flow on 16-wide\n"); } @@ -3872,7 +3872,7 @@ fs_visitor::generate_code() assert(intel->gen == 6); gen6_IF(p, inst->conditional_mod, src[0], src[1]); } else { - brw_IF(p, BRW_EXECUTE_8); + brw_IF(p, c->dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8); } if_depth_in_loop[loop_stack_depth]++; break; |