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authorBen Widawsky <[email protected]>2014-12-23 13:59:16 -0800
committerBen Widawsky <[email protected]>2015-02-07 08:08:59 -0800
commit7ea1e3749738c63388d3bcca327e4e4dd28f17b8 (patch)
tree0647f15a5b8743ad73e812769f8f64f4339b37dc /src/mesa/drivers/dri
parentefde74c89dd8596b4cc0dfd9601e55832833f20e (diff)
i965: Add more stringent blitter assertions
Blits to or from a y-tiled surface must always be a multiple of the tile size. From page 16 of the HSW PRM (https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16) "The pitch of a tiled enclosing region must be an integral number of tile widths" Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index e919528894a..9500bd70e81 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -307,6 +307,9 @@ intelEmitCopyBlit(struct brw_context *brw,
if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
return false;
+ assert(!dst_y_tiled || (dst_pitch % 128) == 0);
+ assert(!src_y_tiled || (src_pitch % 128) == 0);
+
/* do space check before going any further */
do {
aper_array[0] = brw->batch.bo;