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authorFrancisco Jerez <[email protected]>2013-11-22 18:35:46 -0800
committerFrancisco Jerez <[email protected]>2015-02-10 19:09:25 +0200
commit1b224290fbf8f4f4ccf933a6281276931ccec9b8 (patch)
treed68a31523790f50104604f01cb2dad1cde3c9b49 /src/mesa/drivers/dri
parent46b03d5400794736e04eee5d373673309ba286ad (diff)
i965/gen7-8: Implement glMemoryBarrier().
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c40
-rw-r--r--src/mesa/drivers/dri/i965/intel_reg.h1
2 files changed, 41 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index d9a3f057fec..aed595e9740 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -44,6 +44,7 @@
#include "brw_context.h"
#include "brw_shader.h"
#include "brw_wm.h"
+#include "intel_batchbuffer.h"
static unsigned
get_new_program_id(struct intel_screen *screen)
@@ -179,6 +180,43 @@ brwProgramStringNotify(struct gl_context *ctx,
return true;
}
+static void
+brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
+{
+ struct brw_context *brw = brw_context(ctx);
+ unsigned bits = (PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+ PIPE_CONTROL_NO_WRITE |
+ PIPE_CONTROL_CS_STALL);
+ assert(brw->gen >= 7 && brw->gen <= 8);
+
+ if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
+ GL_ELEMENT_ARRAY_BARRIER_BIT |
+ GL_COMMAND_BARRIER_BIT))
+ bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+
+ if (barriers & GL_UNIFORM_BARRIER_BIT)
+ bits |= (PIPE_CONTROL_TC_FLUSH |
+ PIPE_CONTROL_CONST_CACHE_INVALIDATE);
+
+ if (barriers & GL_TEXTURE_FETCH_BARRIER_BIT)
+ bits |= PIPE_CONTROL_TC_FLUSH;
+
+ if (barriers & GL_TEXTURE_UPDATE_BARRIER_BIT)
+ bits |= PIPE_CONTROL_WRITE_FLUSH;
+
+ if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
+ bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_WRITE_FLUSH);
+
+ /* Typed surface messages are handled by the render cache on IVB, so we
+ * need to flush it too.
+ */
+ if (brw->gen == 7 && !brw->is_haswell)
+ bits |= PIPE_CONTROL_WRITE_FLUSH;
+
+ brw_emit_pipe_control_flush(brw, bits);
+}
+
void
brw_add_texrect_params(struct gl_program *prog)
{
@@ -236,6 +274,8 @@ void brwInitFragProgFuncs( struct dd_function_table *functions )
functions->NewShader = brw_new_shader;
functions->LinkShader = brw_link_shader;
+
+ functions->MemoryBarrier = brw_memory_barrier;
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index 5ac0180dc5c..8b630c5fc54 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -70,6 +70,7 @@
#define PIPE_CONTROL_ISP_DIS (1 << 9)
#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8)
/* GT */
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE (1 << 5)
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2)