diff options
author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-06-06 20:32:35 -0700 |
---|---|---|
committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-07-15 16:01:43 -0700 |
commit | 26282a01f5a5045760d4dbe753b48de5a6648d8e (patch) | |
tree | 44ea00f4326a8654f5bc5bd3302e692ec6fe854f /src/mesa/drivers/dri | |
parent | 7e951cd56228a726397d59286bf97287df36dc27 (diff) |
i965/gen8: Use the generic ISL-based path for renderbuffer surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 16 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen8_surface_state.c | 249 |
2 files changed, 2 insertions, 263 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 9003d30057e..bdcb8346613 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -324,22 +324,6 @@ void gen8_upload_3dstate_so_buffers(struct brw_context *brw); void gen8_init_vtable_surface_functions(struct brw_context *brw); -unsigned gen8_surface_tiling_mode(uint32_t tiling); -unsigned gen8_vertical_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type); -unsigned gen8_horizontal_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type); -uint32_t *gen8_allocate_surface_state(struct brw_context *brw, - uint32_t *out_offset, int index); - -void gen8_emit_fast_clear_color(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t *surf); -uint32_t gen8_get_aux_mode(const struct brw_context *brw, - const struct intel_mipmap_tree *mt); - /* brw_sampler_state.c */ void brw_emit_sampler_state(struct brw_context *brw, uint32_t *sampler_state, diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index ed262714abc..00e4c4836aa 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -42,83 +42,7 @@ #include "brw_wm.h" #include "isl/isl.h" -static uint32_t -surface_tiling_resource_mode(uint32_t tr_mode) -{ - switch (tr_mode) { - case INTEL_MIPTREE_TRMODE_YF: - return GEN9_SURFACE_TRMODE_TILEYF; - case INTEL_MIPTREE_TRMODE_YS: - return GEN9_SURFACE_TRMODE_TILEYS; - default: - return GEN9_SURFACE_TRMODE_NONE; - } -} - -uint32_t -gen8_surface_tiling_mode(uint32_t tiling) -{ - switch (tiling) { - case I915_TILING_X: - return GEN8_SURFACE_TILING_X; - case I915_TILING_Y: - return GEN8_SURFACE_TILING_Y; - default: - return GEN8_SURFACE_TILING_NONE; - } -} - -unsigned -gen8_vertical_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type) -{ - /* On Gen9+ vertical alignment is ignored for 1D surfaces and when - * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value. - */ - if (brw->gen > 8 && - (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE || - surf_type == BRW_SURFACE_1D)) - return GEN8_SURFACE_VALIGN_4; - - switch (mt->valign) { - case 4: - return GEN8_SURFACE_VALIGN_4; - case 8: - return GEN8_SURFACE_VALIGN_8; - case 16: - return GEN8_SURFACE_VALIGN_16; - default: - unreachable("Unsupported vertical surface alignment."); - } -} - -unsigned -gen8_horizontal_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type) -{ - /* On Gen9+ horizontal alignment is ignored when tr_mode is not - * TRMODE_NONE. Set to an arbitrary non-reserved value. - */ - if (brw->gen > 8 && - (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE || - gen9_use_linear_1d_layout(brw, mt))) - return GEN8_SURFACE_HALIGN_4; - - switch (mt->halign) { - case 4: - return GEN8_SURFACE_HALIGN_4; - case 8: - return GEN8_SURFACE_HALIGN_8; - case 16: - return GEN8_SURFACE_HALIGN_16; - default: - unreachable("Unsupported horizontal surface alignment."); - } -} - -uint32_t * +static uint32_t * gen8_allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index) { @@ -169,44 +93,6 @@ gen8_emit_buffer_surface_state(struct brw_context *brw, } } -void -gen8_emit_fast_clear_color(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t *surf) -{ - if (brw->gen >= 9) { - surf[12] = mt->gen9_fast_clear_color.ui[0]; - surf[13] = mt->gen9_fast_clear_color.ui[1]; - surf[14] = mt->gen9_fast_clear_color.ui[2]; - surf[15] = mt->gen9_fast_clear_color.ui[3]; - } else - surf[7] |= mt->fast_clear_color_value; -} - -uint32_t -gen8_get_aux_mode(const struct brw_context *brw, - const struct intel_mipmap_tree *mt) -{ - if (mt->mcs_mt == NULL) - return GEN8_SURFACE_AUX_MODE_NONE; - - /* - * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE): - * "When MCS is enabled for non-MSRT, HALIGN_16 must be used" - * - * From the hardware spec for GEN9: - * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN - * 16 must be used." - */ - if (brw->gen >= 9 || mt->num_samples == 1) - assert(mt->halign == 16); - - if (intel_miptree_is_lossless_compressed(brw, mt)) - return GEN9_SURFACE_AUX_MODE_CCS_E; - - return GEN8_SURFACE_AUX_MODE_MCS; -} - /** * Creates a null surface. * @@ -231,142 +117,11 @@ gen8_emit_null_surface_state(struct brw_context *brw, SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT); } -/** - * Sets up a surface state structure to point at the given region. - * While it is only used for the front/back buffer currently, it should be - * usable for further buffers when doing ARB_draw_buffer support. - */ -static uint32_t -gen8_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, unsigned unit /* unused */, - uint32_t surf_index) -{ - struct gl_context *ctx = &brw->ctx; - struct intel_renderbuffer *irb = intel_renderbuffer(rb); - struct intel_mipmap_tree *mt = irb->mt; - unsigned width = mt->logical_width0; - unsigned height = mt->logical_height0; - unsigned pitch = mt->pitch; - uint32_t tiling = mt->tiling; - unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode); - uint32_t format = 0; - uint32_t surf_type; - uint32_t offset; - bool is_array = false; - int depth = MAX2(irb->layer_count, 1); - const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ? - irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1)); - GLenum gl_target = - rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - const uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE; - - intel_miptree_used_for_rendering(mt); - - switch (gl_target) { - case GL_TEXTURE_CUBE_MAP_ARRAY: - case GL_TEXTURE_CUBE_MAP: - surf_type = BRW_SURFACE_2D; - is_array = true; - depth *= 6; - break; - case GL_TEXTURE_3D: - depth = MAX2(irb->mt->logical_depth0, 1); - /* fallthrough */ - default: - surf_type = translate_tex_target(gl_target); - is_array = _mesa_is_array_texture(mt->target); - break; - } - - /* _NEW_BUFFERS */ - /* Render targets can't use IMS layout. */ - assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); - assert(brw_render_target_supported(brw, rb)); - mesa_format rb_format = _mesa_get_render_format(ctx, - intel_rb_format(irb)); - format = brw->render_target_format[rb_format]; - if (unlikely(!brw->format_supported_as_render_target[rb_format])) - _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", - __func__, _mesa_get_format_name(rb_format)); - - struct intel_mipmap_tree *aux_mt = mt->mcs_mt; - const uint32_t aux_mode = gen8_get_aux_mode(brw, mt); - - uint32_t *surf = gen8_allocate_surface_state(brw, &offset, surf_index); - - surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | - (is_array ? GEN7_SURFACE_IS_ARRAY : 0) | - (format << BRW_SURFACE_FORMAT_SHIFT) | - gen8_vertical_alignment(brw, mt, surf_type) | - gen8_horizontal_alignment(brw, mt, surf_type) | - gen8_surface_tiling_mode(tiling); - - surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2; - - surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) | - SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT); - - surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT | - (pitch - 1); /* Surface Pitch */ - - surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT | - (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; - - if (mt->format != MESA_FORMAT_S_UINT8) - surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout); - - surf[5] = irb->mt_level - irb->mt->first_level; - - if (brw->gen >= 9) { - surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE); - /* Disable Mip Tail by setting a large value. */ - surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD); - } - - if (aux_mt) { - uint32_t tile_w, tile_h; - assert(aux_mt->tiling == I915_TILING_Y); - intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode, - aux_mt->cpp, &tile_w, &tile_h); - surf[6] = SET_FIELD(aux_mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) | - SET_FIELD((aux_mt->pitch / tile_w) - 1, - GEN8_SURFACE_AUX_PITCH) | - aux_mode; - } - - gen8_emit_fast_clear_color(brw, mt, surf); - surf[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | - SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | - SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | - SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); - - assert(mt->offset % mt->cpp == 0); - *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */ - - if (aux_mt) { - *((uint64_t *) &surf[10]) = aux_mt->bo->offset64; - drm_intel_bo_emit_reloc(brw->batch.bo, - offset + 10 * 4, - aux_mt->bo, 0, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - } - - drm_intel_bo_emit_reloc(brw->batch.bo, - offset + 8 * 4, - mt->bo, - mt->offset, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); - - return offset; -} - void gen8_init_vtable_surface_functions(struct brw_context *brw) { brw->vtbl.update_texture_surface = brw_update_texture_surface; - brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface; + brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state; brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state; } |