summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri
diff options
context:
space:
mode:
authorEric Anholt <[email protected]>2014-04-25 11:20:57 -0700
committerEric Anholt <[email protected]>2014-05-01 15:12:26 -0700
commit9791eb4280a5814de9af6d9197d947221342dc4e (patch)
tree6f195926578364da5aed89e29960af80f1adc9e5 /src/mesa/drivers/dri
parentea2cac01e875a9953496c03057480fc3bf7fbc0e (diff)
i965: Move intel_region_get_tile_masks() to be a miptree function.
All the consumers are doing it on a miptree. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c14
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c35
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h5
-rw-r--r--src/mesa/drivers/dri/i965/intel_regions.c33
-rw-r--r--src/mesa/drivers/dri/i965/intel_regions.h5
6 files changed, 47 insertions, 48 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 57ff30a7fb0..121fe1583a3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -142,8 +142,7 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
struct intel_region *region = mt->region;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y,
- map_stencil_as_y_tiled);
+ intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled);
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index a6b108b6983..aafb3fe2b9a 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -179,13 +179,13 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t tile_mask_x = 0, tile_mask_y = 0;
if (depth_mt) {
- intel_region_get_tile_masks(depth_mt->region,
- &tile_mask_x, &tile_mask_y, false);
+ intel_miptree_get_tile_masks(depth_mt, &tile_mask_x, &tile_mask_y, false);
if (intel_miptree_slice_has_hiz(depth_mt, depth_level, depth_layer)) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
- intel_region_get_tile_masks(depth_mt->hiz_mt->region,
- &hiz_tile_mask_x, &hiz_tile_mask_y, false);
+ intel_miptree_get_tile_masks(depth_mt->hiz_mt,
+ &hiz_tile_mask_x, &hiz_tile_mask_y,
+ false);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
@@ -205,9 +205,9 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
tile_mask_y |= 63;
} else {
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
- intel_region_get_tile_masks(stencil_mt->region,
- &stencil_tile_mask_x,
- &stencil_tile_mask_y, false);
+ intel_miptree_get_tile_masks(stencil_mt,
+ &stencil_tile_mask_x,
+ &stencil_tile_mask_y, false);
tile_mask_x |= stencil_tile_mask_x;
tile_mask_y |= stencil_tile_mask_y;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c24cfcea4bc..2802043b2b3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -976,6 +976,39 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
}
/**
+ * This function computes masks that may be used to select the bits of the X
+ * and Y coordinates that indicate the offset within a tile. If the region is
+ * untiled, the masks are set to 0.
+ */
+void
+intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
+ uint32_t *mask_x, uint32_t *mask_y,
+ bool map_stencil_as_y_tiled)
+{
+ int cpp = mt->region->cpp;
+ uint32_t tiling = mt->region->tiling;
+
+ if (map_stencil_as_y_tiled)
+ tiling = I915_TILING_Y;
+
+ switch (tiling) {
+ default:
+ assert(false);
+ case I915_TILING_NONE:
+ *mask_x = *mask_y = 0;
+ break;
+ case I915_TILING_X:
+ *mask_x = 512 / cpp - 1;
+ *mask_y = 7;
+ break;
+ case I915_TILING_Y:
+ *mask_x = 128 / cpp - 1;
+ *mask_y = 31;
+ break;
+ }
+}
+
+/**
* Rendering with tiled buffers requires that the base address of the buffer
* be aligned to a page boundary. For renderbuffers, and sometimes with
* textures, we may want the surface to point at a texture image level that
@@ -995,7 +1028,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y, false);
+ intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, false);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 78ccfc6cfe2..d09d09bd64c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -536,6 +536,11 @@ void
intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
int *width, int *height, int *depth);
+void
+intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
+ uint32_t *mask_x, uint32_t *mask_y,
+ bool map_stencil_as_y_tiled);
+
uint32_t
intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
GLuint level, GLuint slice,
diff --git a/src/mesa/drivers/dri/i965/intel_regions.c b/src/mesa/drivers/dri/i965/intel_regions.c
index d891e094cec..a8d16cdb1a8 100644
--- a/src/mesa/drivers/dri/i965/intel_regions.c
+++ b/src/mesa/drivers/dri/i965/intel_regions.c
@@ -278,39 +278,6 @@ intel_region_release(struct intel_region **region_handle)
}
/**
- * This function computes masks that may be used to select the bits of the X
- * and Y coordinates that indicate the offset within a tile. If the region is
- * untiled, the masks are set to 0.
- */
-void
-intel_region_get_tile_masks(const struct intel_region *region,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled)
-{
- int cpp = region->cpp;
- uint32_t tiling = region->tiling;
-
- if (map_stencil_as_y_tiled)
- tiling = I915_TILING_Y;
-
- switch (tiling) {
- default:
- assert(false);
- case I915_TILING_NONE:
- *mask_x = *mask_y = 0;
- break;
- case I915_TILING_X:
- *mask_x = 512 / cpp - 1;
- *mask_y = 7;
- break;
- case I915_TILING_Y:
- *mask_x = 128 / cpp - 1;
- *mask_y = 31;
- break;
- }
-}
-
-/**
* Compute the offset (in bytes) from the start of the region to the given x
* and y coordinate. For tiled regions, caller must ensure that x and y are
* multiples of the tile size.
diff --git a/src/mesa/drivers/dri/i965/intel_regions.h b/src/mesa/drivers/dri/i965/intel_regions.h
index eb2123e95ed..ff7a5f06fd2 100644
--- a/src/mesa/drivers/dri/i965/intel_regions.h
+++ b/src/mesa/drivers/dri/i965/intel_regions.h
@@ -103,11 +103,6 @@ void intel_region_reference(struct intel_region **dst,
void intel_region_release(struct intel_region **ib);
-void
-intel_region_get_tile_masks(const struct intel_region *region,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled);
-
uint32_t
intel_region_get_aligned_offset(const struct intel_region *region, uint32_t x,
uint32_t y, bool map_stencil_as_y_tiled);