diff options
| author | Eric Anholt <[email protected]> | 2011-01-05 14:48:05 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2011-01-05 14:50:27 -0800 |
| commit | 39cc0ee3eaf0d0cae70d91ae33961053782662c8 (patch) | |
| tree | 0de01fd73a939aed8a17651aacc16d0626e02894 /src/mesa/drivers/dri | |
| parent | 973e821a633031fe5a8608b50beabb10af21430e (diff) | |
i915: Enable LOD preclamping on 8xx like on 915/965.
Fixes lodclamp-between and lodclamp-between-max.
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i915/i830_reg.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i830_texstate.c | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h index 41442490706..99ee1bb4e90 100644 --- a/src/mesa/drivers/dri/i915/i830_reg.h +++ b/src/mesa/drivers/dri/i915/i830_reg.h @@ -585,6 +585,8 @@ #define TM0S2_VERITCAL_LINE_STRIDE_OFF (1<<12) #define TM0S2_OUTPUT_CHAN_SHIFT 10 #define TM0S2_OUTPUT_CHAN_MASK (3<<10) +#define TM0S2_BASE_MIP_LEVEL_SHIFT 1 +#define TM0S2_LOD_PRECLAMP (1 << 0) #define TM0S3_MIP_FILTER_MASK (0x3<<30) #define TM0S3_MIP_FILTER_SHIFT 30 diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 8340cd8c333..26ce5c375b6 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -266,6 +266,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) maxlod_fixed = U_FIXED(CLAMP(maxlod, 0.0, 11.75), 2); maxlod_fixed = MAX2(maxlod_fixed, (minlod_fixed + 3) >> 2); state[I830_TEXREG_TM0S3] |= maxlod_fixed << TM0S3_MIN_MIP_SHIFT; + state[I830_TEXREG_TM0S2] |= TM0S2_LOD_PRECLAMP; } else { maxlod_fixed = U_FIXED(CLAMP(maxlod, 0.0, 11), 0); maxlod_fixed = MAX2(maxlod_fixed, (minlod_fixed + 15) >> 4); |