dri/radeon: drop obsolete radeon_{dri,macros}.h headers

Both have been unused for at least a couple of years.
For example the last user of radeon_macros.h was removed with

commit 8c11f0a88300f7bc3f05a12789c781ba0f4b3cc6
Author: Eric Anholt <[email protected]>
Date:   Fri Oct 14 13:27:02 2011 -0700

    radeon: Drop the legacy BO manager code.

Cc: Marek Olšák <[email protected]>
Cc: Michel Dänzer <[email protected]>
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>

4 files changed, 2 insertions, 245 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 9a6fbbdb051..044e2122320 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "swrast/s_renderbuffer.h"
 
 #include "radeon_chipset.h"
-#include "radeon_macros.h"
 #include "radeon_screen.h"
 #include "radeon_common.h"
 #include "radeon_common_context.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 9b77627b857..b5cc075bbad 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -40,8 +40,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  * IMPORTS: these headers contain all the DRI, X and kernel-related
  * definitions that we need.
  */
+#include <xf86drm.h>
+#include <radeon_drm.h>
 #include "dri_util.h"
-#include "radeon_dri.h"
 #include "radeon_chipset.h"
 #include "radeon_reg.h"
 #include "drm_sarea.h"
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.h b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
deleted file mode 100644
index dc513721075..00000000000
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- * \file server/radeon_dri.h
- * \brief Radeon server-side structures.
- * 
- * \author Kevin E. Martin <[email protected]>
- * \author Rickard E. Faith <[email protected]>
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- *                VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _RADEON_DRI_
-#define _RADEON_DRI_
-
-#include "xf86drm.h"
-#include "drm.h"
-#include "radeon_drm.h"
-
-/* DRI Driver defaults */
-#define RADEON_DEFAULT_CP_PIO_MODE    RADEON_CSQ_PRIPIO_INDPIO
-#define RADEON_DEFAULT_CP_BM_MODE     RADEON_CSQ_PRIBM_INDBM
-#define RADEON_DEFAULT_AGP_MODE       1
-#define RADEON_DEFAULT_AGP_FAST_WRITE 0
-#define RADEON_DEFAULT_AGP_SIZE       8 /* MB (must be 2^n and > 4MB) */
-#define RADEON_DEFAULT_RING_SIZE      1 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_BUFFER_SIZE    2 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_AGP_TEX_SIZE   1 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_CP_TIMEOUT     10000  /* usecs */
-#define RADEON_DEFAULT_PAGE_FLIP      0 /* page flipping diabled */
-#define RADEON_BUFFER_ALIGN           0x00000fff
-
-/**
- * \brief Radeon DRI driver private data.
- */
-typedef struct {
-    /**
-     * \name DRI screen private data
-     */
-    /*@{*/
-    int           deviceID;	 /**< \brief PCI device ID */
-    int           width;	 /**< \brief width in pixels of display */
-    int           height;	 /**< \brief height in scanlines of display */
-    int           depth;	 /**< \brief depth of display (8, 15, 16, 24) */
-    int           bpp;		 /**< \brief bit depth of display (8, 16, 24, 32) */
-
-    int           IsPCI;	 /**< \brief is current card a PCI card? */
-    int           AGPMode;	 /**< \brief AGP mode */
-
-    int           frontOffset;   /**< \brief front buffer offset */
-    int           frontPitch;	 /**< \brief front buffer pitch */
-    int           backOffset;    /**< \brief shared back buffer offset */
-    int           backPitch;     /**< \brief shared back buffer pitch */
-    int           depthOffset;   /**< \brief shared depth buffer offset */
-    int           depthPitch;    /**< \brief shared depth buffer pitch */
-    int           textureOffset; /**< \brief start of texture data in frame buffer */
-    int           textureSize;   /**< \brief size of texture date */
-    int           log2TexGran;   /**< \brief log2 texture granularity */
-    /*@}*/
-
-    /**
-     * \name MMIO register data
-     */
-    /*@{*/
-    drm_handle_t     registerHandle; /**< \brief MMIO register map size */
-    drmSize       registerSize;   /**< \brief MMIO register map handle */
-    /*@}*/
-
-    /**
-     * \name CP in-memory status information
-     */
-    /*@{*/
-    drm_handle_t     statusHandle;   /**< \brief status map handle */
-    drmSize       statusSize;     /**< \brief status map size */
-    /*@}*/
-
-    /**
-     * \name CP AGP Texture data
-     */
-    /*@{*/
-    drm_handle_t     gartTexHandle;   /**< \brief AGP texture area map handle */
-    drmSize       gartTexMapSize;  /**< \brief AGP texture area map size */
-    int           log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */
-    int           gartTexOffset;   /**< \brief AGP texture area offset in AGP space */
-    /*@}*/
-
-    unsigned int  sarea_priv_offset; /**< \brief offset of the private SAREA data*/
-} RADEONDRIRec, *RADEONDRIPtr;
-
-#endif
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_macros.h b/src/mesa/drivers/dri/radeon/server/radeon_macros.h
deleted file mode 100644
index 355262c9bab..00000000000
--- a/src/mesa/drivers/dri/radeon/server/radeon_macros.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- * \file server/radeon_macros.h
- * \brief Macros for Radeon MMIO operation.
- *
- * \authors Kevin E. Martin <[email protected]>
- * \authors Rickard E. Faith <[email protected]>
- * \authors Alan Hourihane <[email protected]>
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- *                VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _RADEON_MACROS_H_
-#define _RADEON_MACROS_H_
-
-#include <mmio.h>
-
-#  define MMIO_IN8(base, offset) \
-	*(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
-#  define MMIO_IN32(base, offset) \
-	read_MMIO_LE32(base, offset)
-#  define MMIO_OUT8(base, offset, val) \
-	*(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
-#  define MMIO_OUT32(base, offset, val) \
-	*(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
-
-
-				/* Memory mapped register access macros */
-#define INREG8(addr)        MMIO_IN8(RADEONMMIO, addr)
-#define INREG(addr)         MMIO_IN32(RADEONMMIO, addr)
-#define OUTREG8(addr, val)  MMIO_OUT8(RADEONMMIO, addr, val)
-#define OUTREG(addr, val)   MMIO_OUT32(RADEONMMIO, addr, val)
-
-#define ADDRREG(addr)       ((volatile GLuint *)(pointer)(RADEONMMIO + (addr)))
-
-
-#define OUTREGP(addr, val, mask)					\
-do {									\
-    GLuint tmp = INREG(addr);						\
-    tmp &= (mask);							\
-    tmp |= (val);							\
-    OUTREG(addr, tmp);							\
-} while (0)
-
-#define INPLL(dpy, addr) RADEONINPLL(dpy, addr)
-
-#define OUTPLL(addr, val)						\
-do {									\
-    OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |			\
-				      RADEON_PLL_WR_EN));		\
-    OUTREG(RADEON_CLOCK_CNTL_DATA, val);				\
-} while (0)
-
-#define OUTPLLP(dpy, addr, val, mask)					\
-do {									\
-    GLuint tmp = INPLL(dpy, addr);					\
-    tmp &= (mask);							\
-    tmp |= (val);							\
-    OUTPLL(addr, tmp);							\
-} while (0)
-
-#define OUTPAL_START(idx)						\
-do {									\
-    OUTREG8(RADEON_PALETTE_INDEX, (idx));				\
-} while (0)
-
-#define OUTPAL_NEXT(r, g, b)						\
-do {									\
-    OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));	\
-} while (0)
-
-#define OUTPAL_NEXT_CARD32(v)						\
-do {									\
-    OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff));			\
-} while (0)
-
-#define OUTPAL(idx, r, g, b)						\
-do {									\
-    OUTPAL_START((idx));						\
-    OUTPAL_NEXT((r), (g), (b));						\
-} while (0)
-
-#define INPAL_START(idx)						\
-do {									\
-    OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);				\
-} while (0)
-
-#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
-
-#define PAL_SELECT(idx)							\
-do {									\
-    if (!idx) {								\
-	OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &		\
-	       (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL);			\
-    } else {								\
-	OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |		\
-	       RADEON_DAC2_PALETTE_ACC_CTL);				\
-    }									\
-} while (0)
-
-
-#endif