Update DRI drivers to current DRI CVS and make them work.

author: Jon Smirl <[email protected]> 2003-10-21 06:05:39 +0000
committer: Jon Smirl <[email protected]> 2003-10-21 06:05:39 +0000
commit: bcc6eddd335e97d49ed2ef3a1440f94d58dce12d (patch)
tree: ff4883dd4da6ce65500940aebe2c268716311fe6 /src/mesa/drivers/dri/radeon
parent: 906449753f126f74ad3321d0af897f6609880c17 (diff)
27 files changed, 422 insertions, 463 deletions
diff --git a/src/mesa/drivers/dri/radeon/Makefile.X11 b/src/mesa/drivers/dri/radeon/Makefile.X11
index 57ef24e8fba..19dabce262c 100644
--- a/src/mesa/drivers/dri/radeon/Makefile.X11
+++ b/src/mesa/drivers/dri/radeon/Makefile.X11
@@ -1,4 +1,4 @@
-# $Id: Makefile.X11,v 1.2 2003/10/20 02:17:33 jonsmirl Exp $
+# $Id: Makefile.X11,v 1.3 2003/10/21 06:05:49 jonsmirl Exp $
 
 # Mesa 3-D graphics library
 # Version:  5.0
@@ -49,7 +49,8 @@ DRIVER_SOURCES = radeon_context.c \
 		 ../common/mm.c \
 		 ../common/utils.c \
 		 ../common/texmem.c \
-		 ../common/vblank.c
+		 ../common/vblank.c \
+		 ../common/xmlconfig.c
 
 SUBSET_DRIVER_SOURCES = \
 		radeon_subset_bitmap.c \
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 835cecbc3a0..5604d9c8c21 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.7 2003/02/08 21:26:45 dawes Exp $ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -69,6 +69,25 @@ int RADEON_DEBUG = (0);
 #endif
 
 
+/* Radeon configuration
+ */
+#include "xmlpool.h"
+
+const char __driConfigOptions[] =
+DRI_CONF_BEGIN
+    DRI_CONF_SECTION_PERFORMANCE
+        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
+        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
+        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
+    DRI_CONF_SECTION_END
+    DRI_CONF_SECTION_QUALITY
+        DRI_CONF_PREFERRED_BPT(0,"0,16,32")
+    DRI_CONF_SECTION_END
+    DRI_CONF_SECTION_DEBUG
+        DRI_CONF_NO_RAST(false)
+    DRI_CONF_SECTION_END
+DRI_CONF_END;
+const GLuint __driNConfigOptions = 5;
 
 /* Return the width and height of the given buffer.
  */
@@ -102,8 +121,7 @@ static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
       offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
 				     agp_mode );
 
-      sprintf( & buffer[ offset ], "%s %sTCL",
-	       ( rmesa->dri.drmMinor < 3 ) ? " DRM-COMPAT" : "",
+      sprintf( & buffer[ offset ], "%sTCL",
 	       !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
 	       ? "" : "NO-" );
 
@@ -229,6 +247,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    radeonContextPtr rmesa;
    GLcontext *ctx, *shareCtx;
    int i;
+   int tcl_mode, fthrottle_mode, preferred_bpt;
 
    assert(glVisual);
    assert(driContextPriv);
@@ -258,13 +277,11 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    rmesa->dri.hwContext = driContextPriv->hHWContext;
    rmesa->dri.hwLock = &sPriv->pSAREA->lock;
    rmesa->dri.fd = sPriv->fd;
+   rmesa->dri.drmMinor = sPriv->drmMinor;
 
-   /* If we don't have 1.3, fallback to the 1.1 interfaces.
-    */
-   if (getenv("RADEON_COMPAT") || sPriv->drmMinor < 3 ) 
-      rmesa->dri.drmMinor = 1;
-   else
-      rmesa->dri.drmMinor = sPriv->drmMinor;
+   /* Parse configuration files */
+   driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
+			screen->driScreen->myNum, "radeon");
 
    rmesa->radeonScreen = screen;
    rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
@@ -291,6 +308,9 @@ radeonCreateContext( const __GLcontextModes *glVisual,
       driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
 					& rmesa->c_textureSwaps );
    }
+   preferred_bpt = driQueryOptioni (&rmesa->optionCache, "preferred_bpt");
+   rmesa->default32BitTextures =
+       ( ( preferred_bpt == 0 && screen->cpp == 4 ) || preferred_bpt == 32 );
 
    rmesa->swtcl.RenderIndex = ~0;
    rmesa->lost_context = 1;
@@ -338,7 +358,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
       MIN2( ctx->Const.MaxArrayLockSize, 
  	    RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); 
 
-   rmesa->boxes = (getenv("LIBGL_PERFORMANCE_BOXES") != NULL);
+   rmesa->boxes = 0;
 
    /* Initialize the software rasterizer and helper modules.
     */
@@ -392,22 +412,24 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    radeonInitState( rmesa );
    radeonInitSwtcl( ctx );
 
+   fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
    rmesa->iw.irq_seq = -1;
    rmesa->irqsEmitted = 0;
-   rmesa->do_irqs = (rmesa->radeonScreen->irq && !getenv("RADEON_NO_IRQS"));
+   rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
+		     fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 
-   rmesa->do_usleeps = !getenv("RADEON_NO_USLEEPS");
-
-   rmesa->vblank_flags = (rmesa->do_irqs)
-       ? driGetDefaultVBlankFlags() : VBLANK_FLAG_NO_IRQ;
+   rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 
+   rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
+       ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
 #ifndef _SOLO
-   rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( "__glXGetUST" );
-   if ( rmesa->get_ust == NULL ) 
-#endif
-   {
+   rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( (const GLubyte *) "__glXGetUST" );
+   if ( rmesa->get_ust == NULL ) {
       rmesa->get_ust = get_ust_nop;
    }
+#else
+   rmesa->get_ust = get_ust_nop;
+#endif   
 
    (*rmesa->get_ust)( & rmesa->swap_ust );
 
@@ -417,25 +439,20 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 				       debug_control );
 #endif
 
-   if (getenv("RADEON_NO_RAST")) {
+   tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
+   if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
       fprintf(stderr, "disabling 3D acceleration\n");
       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); 
-   }
-   else if (getenv("RADEON_TCL_FORCE_ENABLE")) {
-      fprintf(stderr, "Enabling TCL support...  this will probably crash\n");
-      fprintf(stderr, "         your card if it isn't capable of TCL!\n");
-      rmesa->radeonScreen->chipset |= RADEON_CHIPSET_TCL;
-   } else if (getenv("RADEON_TCL_FORCE_DISABLE") ||
-	    rmesa->dri.drmMinor < 3 ||
-	    !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
+   } else if (tcl_mode == DRI_CONF_TCL_SW ||
+	      !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
       rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
       fprintf(stderr, "disabling TCL support\n");
       TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); 
    }
 
    if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
-      if (!getenv("RADEON_NO_VTXFMT"))
-	 radeonVtxfmtInit( ctx );
+      if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
+	 radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
 
       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE );
    }
@@ -478,9 +495,11 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
 	 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
       }
 
-      if (!rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
-	 if (!getenv("RADEON_NO_VTXFMT"))
+      if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) {
+	 int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
+	 if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
 	    radeonVtxfmtDestroy( rmesa->glCtx );
+      }
 
       /* free the Mesa context */
       rmesa->glCtx->DriverCtx = NULL;
@@ -497,8 +516,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
           */
          int i;
 
-	 /* this assert is not correct, default textures are always on swap list
-	 assert( is_empty_list( & rmesa->swapped ) ); */
+	 assert( is_empty_list( & rmesa->swapped ) );
 
          for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
 	    driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
@@ -506,6 +524,9 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
          }
       }
 
+      /* free the option cache */
+      driDestroyOptionCache (&rmesa->optionCache);
+
       FREE( rmesa );
    }
 }
@@ -556,11 +577,12 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
 	 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, newCtx->glCtx);
 
       if ( newCtx->dri.drawable != driDrawPriv ) {
+	 driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags );
 	 newCtx->dri.drawable = driDrawPriv;
 	 radeonUpdateWindow( newCtx->glCtx );
 	 radeonUpdateViewportOffset( newCtx->glCtx );
       }
-
+  
       _mesa_make_current2( newCtx->glCtx,
 			   (GLframebuffer *) driDrawPriv->driverPrivate,
 			   (GLframebuffer *) driReadPriv->driverPrivate );
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 5f1f9659e84..69808837ea4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -444,7 +444,7 @@ struct radeon_dma_buffer {
    drmBufPtr buf;
 };
 
-#define GET_START(rvb) (rmesa->radeonScreen->agp_buffer_offset +			\
+#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +			\
 			(rvb)->address - rmesa->dma.buf0_address +	\
 			(rvb)->start)
 
@@ -690,6 +690,7 @@ struct radeon_context {
    unsigned              nr_heaps;
    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
    driTextureObject      swapped;
+   GLboolean             default32BitTextures;
 
 
    /* Rasterization and vertex state:
@@ -769,6 +770,10 @@ struct radeon_context {
     */
    struct radeon_dri_mirror dri;
 
+   /* Configuration cache
+    */
+   driOptionCache optionCache;
+
  
    /* Performance counters
     */
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index a388720aba1..4e1f451e70a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -34,8 +34,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *   Gareth Hughes <[email protected]>
  *   Keith Whitwell <[email protected]>
  */
+
 #include <sched.h>
-#include <errno.h>
+#include <errno.h> 
 
 #include "glheader.h"
 #include "imports.h"
@@ -162,7 +163,6 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
    drmRadeonCmdHeader *cmd;
 
 
-   assert(rmesa->dri.drmMinor >= 3); 
    assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
    
    radeonEmitState( rmesa );
@@ -254,7 +254,6 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
    if (RADEON_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s %d\n", __FUNCTION__, min_nr);
 
-   assert(rmesa->dri.drmMinor >= 3); 
    assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
    
    radeonEmitState( rmesa );
@@ -317,7 +316,6 @@ void radeonEmitVertexAOS( radeonContextPtr rmesa,
    rmesa->ioctl.vertex_offset = offset;
 #else
    drmRadeonCmdHeader *cmd;
-   assert(rmesa->dri.drmMinor >= 3); 
 
    if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
@@ -356,7 +354,6 @@ void radeonEmitAOS( radeonContextPtr rmesa,
    if (RADEON_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
-   assert(rmesa->dri.drmMinor >= 3); 
 
    cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
 						  __FUNCTION__ );
@@ -531,8 +528,6 @@ void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
    int ret;
 
 	      
-   assert (rmesa->dri.drmMinor >= 3);
-
    LOCK_HARDWARE( rmesa );
 
    ret = radeonFlushCmdBufLocked( rmesa, caller );
@@ -691,9 +686,6 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa,
    rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */
    rmesa->dma.current.start = 
       rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7;  
-
-   if ( rmesa->dri.drmMinor < 3 ) 
-      radeonRefillCurrentDmaRegion( rmesa );
 }
 
 void radeonAllocDmaRegionVerts( radeonContextPtr rmesa, 
@@ -719,7 +711,7 @@ static CARD32 radeonGetLastFrame (radeonContextPtr rmesa)
       drmRadeonGetParam gp;
 
       gp.param = RADEON_PARAM_LAST_FRAME;
-      gp.value = &frame;
+      gp.value = (int *)&frame;
       ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM,
 				 &gp, sizeof(gp) );
    } 
@@ -1012,7 +1004,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
 	drmRadeonGetParam gp;
 
 	gp.param = RADEON_PARAM_LAST_CLEAR;
-	gp.value = &clear;
+	gp.value = (int *)&clear;
 	ret = drmCommandWriteRead( rmesa->dri.fd,
 				   DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
       } else
@@ -1154,13 +1146,11 @@ void radeonFlush( GLcontext *ctx )
    if (rmesa->dma.flush)
       rmesa->dma.flush( rmesa );
 
-   if (rmesa->dri.drmMinor >= 3) {
-      if (!is_empty_list(&rmesa->hw.dirty)) 
-	 radeonEmitState( rmesa );
+   if (!is_empty_list(&rmesa->hw.dirty)) 
+      radeonEmitState( rmesa );
    
-      if (rmesa->store.cmd_used)
-	 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
-   }
+   if (rmesa->store.cmd_used)
+      radeonFlushCmdBuf( rmesa, __FUNCTION__ );
 }
 
 /* Make sure all commands have been sent to the hardware and have
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 96a4f9d1123..daf001e048a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -53,8 +53,6 @@ radeonUpdatePageFlipping( radeonContextPtr rmesa )
 {
    int use_back;
 
-   if (rmesa->dri.drmMinor < 3)
-      return;
 
    rmesa->doPageFlip = rmesa->sarea->pfAllowPageFlip;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos.h b/src/mesa/drivers/dri/radeon/radeon_maos.h
index 7e2bd643d34..8c8aa15c59f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos.h
+++ b/src/mesa/drivers/dri/radeon/radeon_maos.h
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos.h,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
index cec05a89d7e..fc55b89b030 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -409,7 +409,7 @@ static void emit_tex_vector( GLcontext *ctx,
 
 
 
-/* Emit any changed arrays to new agp memory, re-emit a packet to
+/* Emit any changed arrays to new GART memory, re-emit a packet to
  * update the arrays.  
  */
 void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index 39b1f575074..b32fd624fa3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index e3b37bf3de9..3bc15bdcb47 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
@@ -32,7 +32,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  *   Keith Whitwell <[email protected]>
  *
  */
-#include <errno.h>
+#include <errno.h> 
 
 #include "glheader.h"
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index ec8ed42d649..8f2042af13f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -48,7 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #ifndef _SOLO
 #include "glxextensions.h"
-#endif 
+#endif
 
 #if 1
 /* Including xf86PciInfo.h introduces a bunch of errors...
@@ -89,32 +89,26 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
       return NULL;
    }
 
-   if ( sPriv->drmMinor < 3 ||
-        getenv("RADEON_COMPAT")) {
-	   fprintf( stderr, "Radeon DRI driver:\n\t"
-		    "Compatibility mode for DRM driver version %d.%d.%d\n\t"
-		    "TCL will be disabled, expect reduced performance\n\t"
-		    "(prefer DRM radeon.o 1.3.x or newer)\n\t", 
-		    sPriv->drmMajor, sPriv->drmMinor, sPriv->drmPatch ); 
-   }
-
+   /* parse information in __driConfigOptions */
+   driParseOptionInfo (&screen->optionCache);
 
    /* This is first since which regions we map depends on whether or
     * not we are using a PCI card.
     */
    screen->IsPCI = dri_priv->IsPCI;
 
-   if (sPriv->drmMinor >= 3) {
+   {
       int ret;
       drmRadeonGetParam gp;
 
-      gp.param = RADEON_PARAM_AGP_BUFFER_OFFSET;
-      gp.value = &screen->agp_buffer_offset;
+      gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
+      gp.value = &screen->gart_buffer_offset;
 
       ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 				 &gp, sizeof(gp));
       if (ret) {
-	 fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_AGP_BUFFER_OFFSET): %d\n", ret);
+	 FREE( screen );
+	 fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 	 return NULL;
       }
 
@@ -166,20 +160,26 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
       return NULL;
    }
 
-   if ( !screen->IsPCI ) {
-      screen->agpTextures.handle = dri_priv->agpTexHandle;
-      screen->agpTextures.size   = dri_priv->agpTexMapSize;
+   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
+      unsigned char *RADEONMMIO = screen->mmio.map;
+
+      screen->gartTextures.handle = dri_priv->gartTexHandle;
+      screen->gartTextures.size   = dri_priv->gartTexMapSize;
       if ( drmMap( sPriv->fd,
-		   screen->agpTextures.handle,
-		   screen->agpTextures.size,
-		   (drmAddressPtr)&screen->agpTextures.map ) ) {
+		   screen->gartTextures.handle,
+		   screen->gartTextures.size,
+		   (drmAddressPtr)&screen->gartTextures.map ) ) {
 	 drmUnmapBufs( screen->buffers );
 	 drmUnmap( screen->status.map, screen->status.size );
 	 drmUnmap( screen->mmio.map, screen->mmio.size );
 	 FREE( screen );
-         __driUtilMessage("%s: IsPCI failed\n", __FUNCTION__);
+	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 	 return NULL;
       }
+
+      screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
+		? INREG( RADEON_AIC_LO_ADDR )
+		: ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
    }
 
    screen->chipset = 0;
@@ -215,21 +215,36 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
    screen->logTexGranularity[RADEON_CARD_HEAP] =
       dri_priv->log2TexGran;
 
-   if ( screen->IsPCI 
-	|| getenv( "RADEON_AGPTEXTURING_FORCE_DISABLE" ) ) {
+   if ( !screen->gartTextures.map
+	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
-      screen->texOffset[RADEON_AGP_HEAP] = 0;
-      screen->texSize[RADEON_AGP_HEAP] = 0;
-      screen->logTexGranularity[RADEON_AGP_HEAP] = 0;
+      screen->texOffset[RADEON_GART_HEAP] = 0;
+      screen->texSize[RADEON_GART_HEAP] = 0;
+      screen->logTexGranularity[RADEON_GART_HEAP] = 0;
    } else {
       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
-      screen->texOffset[RADEON_AGP_HEAP] =
-	 dri_priv->agpTexOffset + RADEON_AGP_TEX_OFFSET;
-      screen->texSize[RADEON_AGP_HEAP] = dri_priv->agpTexMapSize;
-      screen->logTexGranularity[RADEON_AGP_HEAP] =
-	 dri_priv->log2AGPTexGran;
+      screen->texOffset[RADEON_GART_HEAP] = screen->gart_texture_offset;
+      screen->texSize[RADEON_GART_HEAP] = dri_priv->gartTexMapSize;
+      screen->logTexGranularity[RADEON_GART_HEAP] =
+	 dri_priv->log2GARTTexGran;
    }
+#ifndef _SOLO
+   if ( driCompareGLXAPIVersion( 20030813 ) >= 0 ) {
+      PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
+          (PFNGLXSCRENABLEEXTENSIONPROC) glXGetProcAddress( (const GLubyte *) "__glXScrEnableExtension" );
+      void * const psc = sPriv->psc->screenConfigs;
+
+      if ( glx_enable_extension != NULL ) {
+	 if ( screen->irq != 0 ) {
+	    (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
+	    (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
+	    (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
+	 }
 
+	 (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
+      }
+   }
+#endif
    screen->driScreen = sPriv;
    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
    return screen;
@@ -244,14 +259,16 @@ void radeonDestroyScreen( __DRIscreenPrivate *sPriv )
    if (!screen)
       return;
 
-   if ( !screen->IsPCI ) {
-      drmUnmap( screen->agpTextures.map,
-		screen->agpTextures.size );
+   if ( screen->gartTextures.map ) {
+      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
    }
    drmUnmapBufs( screen->buffers );
    drmUnmap( screen->status.map, screen->status.size );
    drmUnmap( screen->mmio.map, screen->mmio.size );
 
+   /* free all option information */
+   driDestroyOptionInfo (&screen->optionCache);
+
    FREE( screen );
    sPriv->private = NULL;
 }
@@ -350,7 +367,7 @@ static struct __DriverAPIRec radeonAPI = {
  * The __driCreateScreen name is the symbol that libGL.so fetches.
  * Return:  pointer to a __DRIscreenPrivate.
  */
-#ifndef _SOLO
+#ifndef _SOLO 
 void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc,
                         int numConfigs, __GLXvisualConfig *config)
 {
@@ -368,10 +385,13 @@ void *__driCreateScreen(struct DRIDriverRec *driver,
 }
 #endif
 
-
 #ifndef _SOLO
-/* This function is called by libGL.so as soon as libGL.so is loaded.
+/**
+ * This function is called by libGL.so as soon as libGL.so is loaded.
  * This is where we'd register new extension functions with the dispatcher.
+ *
+ * \todo This interface has been deprecated, so we should probably remove
+ *       this function before the next XFree86 release.
  */
 void
 __driRegisterExtensions( void )
@@ -381,19 +401,18 @@ __driRegisterExtensions( void )
 
    if ( driCompareGLXAPIVersion( 20030317 ) >= 0 ) {
       glx_enable_extension = (PFNGLXENABLEEXTENSIONPROC)
-	  glXGetProcAddress( "__glXEnableExtension" );
+	  glXGetProcAddress( (const GLubyte *) "__glXEnableExtension" );
 
       if ( glx_enable_extension != NULL ) {
-	 glx_enable_extension( "GLX_SGI_swap_control", GL_FALSE );
-	 glx_enable_extension( "GLX_SGI_video_sync", GL_FALSE );
-	 glx_enable_extension( "GLX_MESA_swap_control", GL_FALSE );
-	 glx_enable_extension( "GLX_MESA_swap_frame_usage", GL_FALSE );
+	 (*glx_enable_extension)( "GLX_SGI_swap_control", GL_FALSE );
+	 (*glx_enable_extension)( "GLX_SGI_video_sync", GL_FALSE );
+	 (*glx_enable_extension)( "GLX_MESA_swap_control", GL_FALSE );
+	 (*glx_enable_extension)( "GLX_MESA_swap_frame_usage", GL_FALSE );
       }
    }
 }
 #endif
 
-
 /**
  * Get information about previous buffer swaps.
  */
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 2c69d8657ae..133c3633c1b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_dri.h"
 #include "radeon_reg.h"
 #include "radeon_sarea.h"
+#include "xmlconfig.h"
 
 
 typedef struct {
@@ -83,7 +84,7 @@ typedef struct {
 
    radeonRegionRec mmio;
    radeonRegionRec status;
-   radeonRegionRec agpTextures;
+   radeonRegionRec gartTextures;
 
    drmBufMapPtr buffers;
 
@@ -91,7 +92,11 @@ typedef struct {
 
    __DRIscreenPrivate *driScreen;
    unsigned int sarea_priv_offset;
-   unsigned int agp_buffer_offset;	/* offset in card memory space */
+   unsigned int gart_buffer_offset;	/* offset in card memory space */
+   unsigned int gart_texture_offset;	/* offset in card memory space */
+
+   /* Configuration cache with default values for all contexts */
+   driOptionCache optionCache;
 } radeonScreenRec, *radeonScreenPtr;
 
 extern radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv );
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 971ea699ea2..0b2a1089b8c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
 /*
  * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
  *
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index 926b1523d62..89db677392d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -67,7 +67,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RADEON_MAX_SETUP	0x40
 
 static void flush_last_swtcl_prim( radeonContextPtr rmesa  );
-static void flush_last_swtcl_prim_compat( radeonContextPtr rmesa );
 
 static struct {
    void                (*emit)( GLcontext *, GLuint, GLuint, void *, GLuint );
@@ -282,7 +281,6 @@ static void radeonRenderStart( GLcontext *ctx )
    }
    
    if (rmesa->dma.flush != 0 && 
-       rmesa->dma.flush != flush_last_swtcl_prim_compat &&
        rmesa->dma.flush != flush_last_swtcl_prim)
       rmesa->dma.flush( rmesa );
 }
@@ -381,7 +379,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 
    if (rmesa->dma.current.buf) {
       struct radeon_dma_region *current = &rmesa->dma.current;
-      GLuint current_offset = (rmesa->radeonScreen->agp_buffer_offset +
+      GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
 			       current->buf->buf->idx * RADEON_BUFFER_SIZE + 
 			       current->start);
 
@@ -408,46 +406,6 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 }
 
 
-static void flush_last_swtcl_prim_compat( radeonContextPtr rmesa )
-{
-   struct radeon_dma_region *current = &rmesa->dma.current;
-
-   if (RADEON_DEBUG & DEBUG_IOCTL)
-      fprintf(stderr, "%s buf %p start %d ptr %d\n", 
-	      __FUNCTION__,
-	      current->buf,
-	      current->start,
-	      current->ptr);
-
-   assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-   assert (current->start + 
-	   rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
-	   current->ptr);
-   assert (current->start == 0);
-
-   rmesa->dma.flush = 0;
-
-   if (current->ptr && current->buf) {
-      assert (current->buf->refcount == 1);
-
-      radeonCompatEmitPrimitive( rmesa,
-				 rmesa->swtcl.vertex_format,
-				 rmesa->swtcl.hw_primitive,
-				 rmesa->swtcl.numverts);
-      
-      /* The buffer has been released:
-       */
-      FREE(current->buf);
-      current->buf = 0;
-      current->start = 0;
-      current->ptr = current->end;
-
-   }
-
-   rmesa->swtcl.numverts = 0;
-}
-
-
 /* Alloc space in the current dma region.
  */
 static __inline void *radeonAllocDmaLowVerts( radeonContextPtr rmesa,
@@ -460,22 +418,18 @@ static __inline void *radeonAllocDmaLowVerts( radeonContextPtr rmesa,
 
    if (!rmesa->dma.flush) {
       rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
-      if (rmesa->dri.drmMinor == 1)
-	 rmesa->dma.flush = flush_last_swtcl_prim_compat;
-      else
-	 rmesa->dma.flush = flush_last_swtcl_prim;
+      rmesa->dma.flush = flush_last_swtcl_prim;
    }
 
    assert( vsize == rmesa->swtcl.vertex_size * 4 );
-   assert( rmesa->dma.flush == flush_last_swtcl_prim ||
-	   rmesa->dma.flush == flush_last_swtcl_prim_compat);
+   assert( rmesa->dma.flush == flush_last_swtcl_prim );
    assert (rmesa->dma.current.start + 
 	   rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 	   rmesa->dma.current.ptr);
 
 
    {
-      char *head = rmesa->dma.current.address + rmesa->dma.current.ptr;
+      GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
       rmesa->dma.current.ptr += bytes;
       rmesa->swtcl.numverts += nverts;
       return head;
@@ -624,7 +578,7 @@ do {									\
 									\
       radeonEmitVertexAOS( rmesa,					\
 			   rmesa->swtcl.vertex_size,			\
-			   (rmesa->radeonScreen->agp_buffer_offset +		\
+			   (rmesa->radeonScreen->gart_buffer_offset +	\
 			    rmesa->swtcl.indexed_verts.buf->buf->idx * 	\
 			    RADEON_BUFFER_SIZE +			\
 			    rmesa->swtcl.indexed_verts.start));		\
@@ -683,15 +637,6 @@ static GLboolean radeon_run_render( GLcontext *ctx,
        ctx->Line.StippleFlag)        /* GH: THIS IS A HACK!!! */
       return GL_TRUE;		
 
-   if (rmesa->dri.drmMinor < 3) {
-      /* drm 1.1 doesn't support vertex primitives starting in the
-       * middle of a buffer.  It doesn't support sane indexed vertices
-       * either.  drm 1.2 fixes both of these problems, but we don't have a
-       * compatibility layer to that version yet.  
-       */
-      return GL_TRUE;
-   }
-
    tnl->Driver.Render.Start( ctx );
 
    if (VB->Elts) {
@@ -952,7 +897,6 @@ static void radeonResetLineStipple( GLcontext *ctx );
 
 #define RADEON_TWOSIDE_BIT	0x01
 #define RADEON_UNFILLED_BIT	0x02
-#define RADEON_OFFSET_BIT	0x04 /* drmMinor == 1 */
 #define RADEON_MAX_TRIFUNC	0x08
 
 
@@ -965,7 +909,7 @@ static struct {
 
 
 #define DO_FALLBACK  0
-#define DO_OFFSET   (IND & RADEON_OFFSET_BIT)
+#define DO_OFFSET    0
 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 #define DO_FLAT      0
@@ -1051,22 +995,6 @@ static struct {
 #define TAG(x) x##_twoside_unfilled
 #include "tnl_dd/t_dd_tritmp.h"
 
-#define IND (RADEON_OFFSET_BIT)
-#define TAG(x) x##_offset
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_TWOSIDE_BIT|RADEON_OFFSET_BIT)
-#define TAG(x) x##_twoside_offset
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_UNFILLED_BIT|RADEON_OFFSET_BIT)
-#define TAG(x) x##_unfilled_offset
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT|RADEON_OFFSET_BIT)
-#define TAG(x) x##_twoside_unfilled_offset
-#include "tnl_dd/t_dd_tritmp.h"
-
 
 static void init_rast_tab( void )
 {
@@ -1074,10 +1002,6 @@ static void init_rast_tab( void )
    init_twoside();
    init_unfilled();
    init_twoside_unfilled();
-   init_offset();
-   init_twoside_offset();
-   init_unfilled_offset();
-   init_twoside_unfilled_offset();
 }
 
 /**********************************************************************/
@@ -1136,8 +1060,6 @@ void radeonChooseRenderState( GLcontext *ctx )
 
    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
-   if ((flags & DD_TRI_OFFSET) &&
-       rmesa->dri.drmMinor == 1)  index |= RADEON_OFFSET_BIT;
 
    if (index != rmesa->swtcl.RenderIndex) {
       tnl->Driver.Render.Points = rast_tab[index].points;
@@ -1300,7 +1222,7 @@ void radeonInitSwtcl( GLcontext *ctx )
    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
    tnl->Driver.Render.BuildVertices = radeonBuildVertices;
 
-   rmesa->swtcl.verts = ALIGN_MALLOC( size * 16 * 4, 32 );
+   rmesa->swtcl.verts = (GLubyte *)ALIGN_MALLOC( size * 16 * 4, 32 );
    rmesa->swtcl.RenderIndex = ~0;
    rmesa->swtcl.render_primitive = GL_TRIANGLES;
    rmesa->swtcl.hw_primitive = 0;
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.h b/src/mesa/drivers/dri/radeon/radeon_tcl.h
index 1e97d32148a..881264a2676 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.h
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.h,v 1.2 2003/02/08 21:26:45 dawes Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index 3adc2a951c6..284efb225ac 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -35,7 +35,7 @@ SOFTWARE.
  *   Gareth Hughes <[email protected]>
  *
  */
-#include <errno.h>
+#include <errno.h> 
 
 #include "glheader.h"
 #include "imports.h"
@@ -112,8 +112,8 @@ static void radeonUploadRectSubImage( radeonContextPtr rmesa,
    height = texImage->Height;
    dstPitch = t->pp_txpitch + 32;
 
-   {	/* FIXME: prefer AGP-texturing if possible */
-      /* Data not in agp memory, or bad pitch.
+   {	/* FIXME: prefer GART-texturing if possible */
+      /* Data not in GART memory, or bad pitch.
        */
       for (done = 0; done < height ; ) {
 	 struct radeon_dma_region region;
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 6dccd311800..0bece3e8b9b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -107,7 +107,7 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
    const struct gl_texture_image *baseImage = tObj->Image[tObj->BaseLevel];
    GLint curOffset;
    GLint i;
-   GLint firstLevel=0, lastLevel=0, numLevels;
+   GLint numLevels;
    GLint log2Width, log2Height, log2Depth;
 
    /* Set the hardware texture format
@@ -127,40 +127,15 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
    }
 
 
-
    /* Compute which mipmap levels we really want to send to the hardware.
-    * This depends on the base image size, GL_TEXTURE_MIN_LOD,
-    * GL_TEXTURE_MAX_LOD, GL_TEXTURE_BASE_LEVEL, and GL_TEXTURE_MAX_LEVEL.
-    * Yes, this looks overly complicated, but it's all needed.
     */
-   switch (tObj->Target) {
-   case GL_TEXTURE_1D:
-   case GL_TEXTURE_2D:
-      firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
-      firstLevel = MAX2(firstLevel, tObj->BaseLevel);
-      lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
-      lastLevel = MAX2(lastLevel, tObj->BaseLevel);
-      lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
-      lastLevel = MIN2(lastLevel, tObj->MaxLevel);
-      lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
-      log2Width = tObj->Image[firstLevel]->WidthLog2;
-      log2Height = tObj->Image[firstLevel]->HeightLog2;
-      log2Depth = 0;
-      break;
-   case GL_TEXTURE_RECTANGLE_NV:
-      firstLevel = lastLevel = 0;
-      log2Width = log2Height = 1; /* ? */
-      log2Depth = 0;
-      break;
-   default:
-      return;
-   }
 
-   /* save these values */
-   t->base.firstLevel = firstLevel;
-   t->base.lastLevel = lastLevel;
+   driCalculateTextureFirstLastLevel( (driTextureObject *) t );
+   log2Width  = tObj->Image[t->base.firstLevel]->WidthLog2;
+   log2Height = tObj->Image[t->base.firstLevel]->HeightLog2;
+   log2Depth  = tObj->Image[t->base.firstLevel]->DepthLog2;
 
-   numLevels = lastLevel - firstLevel + 1;
+   numLevels = t->base.lastLevel - t->base.firstLevel + 1;
 
    assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS);
 
@@ -174,7 +149,7 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
       const struct gl_texture_image *texImage;
       GLuint size;
 
-      texImage = tObj->Image[i + firstLevel];
+      texImage = tObj->Image[i + t->base.firstLevel];
       if ( !texImage )
 	 break;
 
@@ -194,10 +169,12 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
       }
       assert(size > 0);
 
-      if (curOffset & 0x1f) {
-         /* align to 32-byte offset */
-         curOffset = (curOffset + 0x1f) & ~0x1f;
-      }
+
+      /* Align to 32-byte offset.  It is faster to do this unconditionally
+       * (no branch penalty).
+       */
+
+      curOffset = (curOffset + 0x1f) & ~0x1f;
 
       t->image[0][i].x = curOffset % BLIT_WIDTH_BYTES;
       t->image[0][i].y = curOffset / BLIT_WIDTH_BYTES;
@@ -237,17 +214,17 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
    t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
 		      (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
 
-   t->pp_txsize = (((tObj->Image[firstLevel]->Width - 1) << 0) |
-                   ((tObj->Image[firstLevel]->Height - 1) << 16));
+   t->pp_txsize = (((tObj->Image[t->base.firstLevel]->Width - 1) << 0) |
+                   ((tObj->Image[t->base.firstLevel]->Height - 1) << 16));
 
    /* Only need to round to nearest 32 for textures, but the blitter
     * requires 64-byte aligned pitches, and we may/may not need the
     * blitter.   NPOT only!
     */
    if (baseImage->IsCompressed)
-      t->pp_txpitch = (tObj->Image[firstLevel]->Width + 63) & ~(63);
+      t->pp_txpitch = (tObj->Image[t->base.firstLevel]->Width + 63) & ~(63);
    else
-      t->pp_txpitch = ((tObj->Image[firstLevel]->Width * baseImage->TexFormat->TexelBytes) + 63) & ~(63);
+      t->pp_txpitch = ((tObj->Image[t->base.firstLevel]->Width * baseImage->TexFormat->TexelBytes) + 63) & ~(63);
    t->pp_txpitch -= 32;
 
    t->dirty_state = TEX_ALL;
@@ -1500,7 +1477,7 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
       RADEON_FIREVERTICES( rmesa );
       radeonSetTexImages( rmesa, tObj );
       radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
-      if ( !t->base.memBlock /* && !rmesa->prefer_agp_client_texturing  FIXME */ ) {
+      if ( !t->base.memBlock /* && !rmesa->prefer_gart_client_texturing  FIXME */ ) {
 	 fprintf(stderr, "%s: upload failed\n", __FUNCTION__);
 	 return GL_FALSE;
       }
diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c
index b613e9eb434..9af0942898d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c
+++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c,v 1.5 2002/12/16 16:18:59 dawes Exp $ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -937,7 +937,7 @@ static void radeonVtxfmtFlushVertices( GLcontext *ctx, GLuint flags )
  */
 
 
-void radeonVtxfmtInit( GLcontext *ctx )
+void radeonVtxfmtInit( GLcontext *ctx, GLboolean useCodegen )
 {
    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
    GLvertexformat *vfmt = &(rmesa->vb.vtxfmt);
@@ -1034,7 +1034,7 @@ void radeonVtxfmtInit( GLcontext *ctx )
    make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord1fARB );
    make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord1fvARB );
 
-   radeonInitCodegen( &rmesa->vb.codegen );
+   radeonInitCodegen( &rmesa->vb.codegen, useCodegen );
 }
 
 static void free_funcs( struct dynfn *l )
diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h
index 9792fcbb788..78033908238 100644
--- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h
+++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h
@@ -42,7 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 extern void radeonVtxfmtUpdate( GLcontext *ctx );
-extern void radeonVtxfmtInit( GLcontext *ctx );
+extern void radeonVtxfmtInit( GLcontext *ctx, GLboolean useCodegen );
 extern void radeonVtxfmtInvalidate( GLcontext *ctx );
 extern void radeonVtxfmtDestroy( GLcontext *ctx );
 extern void radeonVtxfmtInitChoosers( GLvertexformat *vfmt );
@@ -84,7 +84,7 @@ do {								\
 
 /* 
  */
-void radeonInitCodegen( struct dfn_generators *gen );
+void radeonInitCodegen( struct dfn_generators *gen, GLboolean useCodegen );
 void radeonInitX86Codegen( struct dfn_generators *gen );
 void radeonInitSSECodegen( struct dfn_generators *gen );
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c
index 188e34a4208..04cffb77729 100644
--- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c
+++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c,v 1.2 2002/12/16 16:18:59 dawes Exp $ */
 /**************************************************************************
 
 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
@@ -864,7 +864,7 @@ static struct dynfn *codegen_noop( GLcontext *ctx, int key )
    return 0;
 }
 
-void radeonInitCodegen( struct dfn_generators *gen )
+void radeonInitCodegen( struct dfn_generators *gen, GLboolean useCodegen )
 {
    gen->Vertex3f = codegen_noop;
    gen->Vertex3fv = codegen_noop;
@@ -893,7 +893,7 @@ void radeonInitCodegen( struct dfn_generators *gen )
    gen->MultiTexCoord1fARB = codegen_noop;
    gen->MultiTexCoord1fvARB = codegen_noop;
 
-   if (!getenv("RADEON_NO_CODEGEN")) {
+   if (useCodegen) {
 #if defined(USE_X86_ASM)
       radeonInitX86Codegen( gen );
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c
index 0f2c82bd878..71e74381a5a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c
+++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c,v 1.1 2002/10/30 12:51:58 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c
index 92941ca5f80..59b0db0a5f9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c
+++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c,v 1.2 2002/12/21 17:02:16 dawes Exp $ */
 /**************************************************************************
 
 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
diff --git a/src/mesa/drivers/dri/radeon/server/radeon.h b/src/mesa/drivers/dri/radeon/server/radeon.h
index 4606a0b71e6..808289b140f 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon.h
@@ -108,11 +108,11 @@ typedef struct {
     * \name AGP
     */
    /*@{*/
-   drmSize           agpSize;          /**< \brief AGP map size */
-   drmHandle         agpMemHandle;     /**< \brief AGP map handle */
-   unsigned long     agpOffset;        /**< \brief AGP offset */
-   int               agpMode;          /**< \brief AGP mode */
-   int               agpFastWrite;
+   drmSize           gartSize;          /**< \brief AGP map size */
+   drmHandle         gartMemHandle;     /**< \brief AGP map handle */
+   unsigned long     gartOffset;        /**< \brief AGP offset */
+   int               gartMode;          /**< \brief AGP mode */
+   int               gartFastWrite;
    /*@}*/
 
    /**
@@ -144,11 +144,11 @@ typedef struct {
     * \name CP AGP Texture data
     */
    /*@{*/
-   unsigned long     agpTexStart;      /**< \brief Offset into AGP space */
-   drmHandle         agpTexHandle;     /**< \brief Handle from drmAddMap() */
-   drmSize           agpTexMapSize;    /**< \brief Size of map */
-   int               agpTexSize;       /**< \brief Size of AGP tex space (in MB) */
-   int               log2AGPTexGran;
+   unsigned long     gartTexStart;      /**< \brief Offset into AGP space */
+   drmHandle         gartTexHandle;     /**< \brief Handle from drmAddMap() */
+   drmSize           gartTexMapSize;    /**< \brief Size of map */
+   int               gartTexSize;       /**< \brief Size of AGP tex space (in MB) */
+   int               log2GARTTexGran;
    /*@}*/
 
    int               drmMinor;         /**< \brief DRM device minor number */
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_common.h b/src/mesa/drivers/dri/radeon/server/radeon_common.h
index 0792b5c2e0e..365ecfb9a17 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_common.h
@@ -31,7 +31,7 @@
  * Converted to common header format:
  *   Jens Owen <[email protected]>
  *
- * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drmRadeon.h,v 1.6 2001/04/16 15:02:13 tsi Exp $
+ * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $
  *
  */
 
@@ -70,6 +70,7 @@
 #define DRM_RADEON_INIT_HEAP              0x15
 #define DRM_RADEON_IRQ_EMIT               0x16
 #define DRM_RADEON_IRQ_WAIT               0x17
+#define DRM_RADEON_CP_RESUME              0x18
 #define DRM_RADEON_MAX_DRM_COMMAND_INDEX  0x39
 
 
@@ -94,7 +95,7 @@ typedef struct {
    unsigned long sarea_priv_offset;
    int is_pci;
    int cp_mode;
-   int agp_size;
+   int gart_size;
    int ring_size;
    int usec_timeout;
 
@@ -109,7 +110,7 @@ typedef struct {
    unsigned long ring_offset;
    unsigned long ring_rptr_offset;
    unsigned long buffers_offset;
-   unsigned long agp_textures_offset;
+   unsigned long gart_textures_offset;
 } drmRadeonInit;
 
 typedef struct {
@@ -404,22 +405,22 @@ typedef struct drm_radeon_getparam {
 	void *value;
 } drmRadeonGetParam;
 
-#define RADEON_PARAM_AGP_BUFFER_OFFSET 1
-#define RADEON_PARAM_LAST_FRAME        2
-#define RADEON_PARAM_LAST_DISPATCH     3
-#define RADEON_PARAM_LAST_CLEAR        4
-#define RADEON_PARAM_IRQ_NR            5
-#define RADEON_PARAM_AGP_BASE          6
+#define RADEON_PARAM_GART_BUFFER_OFFSET 1
+#define RADEON_PARAM_LAST_FRAME         2
+#define RADEON_PARAM_LAST_DISPATCH      3
+#define RADEON_PARAM_LAST_CLEAR         4
+#define RADEON_PARAM_IRQ_NR             5
+#define RADEON_PARAM_GART_BASE          6
 
 
-#define RADEON_MEM_REGION_AGP 1
-#define RADEON_MEM_REGION_FB  2
+#define RADEON_MEM_REGION_GART 1
+#define RADEON_MEM_REGION_FB   2
 
 typedef struct drm_radeon_mem_alloc {
 	int region;
 	int alignment;
 	int size;
-	int *region_offset;	/* offset from start of fb or agp */
+	int *region_offset;	/* offset from start of fb or GART */
 } drmRadeonMemAlloc;
 
 typedef struct drm_radeon_mem_free {
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
index 4271aa7da23..a37561457bc 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
@@ -318,7 +318,7 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
    int            s, l;
 
    if (drmAgpAcquire(ctx->drmFD) < 0) {
-      fprintf(stderr, "[agp] AGP not available\n");
+      fprintf(stderr, "[gart] AGP not available\n");
       return 0;
    }
     
@@ -334,40 +334,40 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
    /* Disable fast write entirely - too many lockups.
     */
    mode &= ~RADEON_AGP_MODE_MASK;
-   switch (info->agpMode) {
+   switch (info->gartMode) {
    case 4:          mode |= RADEON_AGP_4X_MODE;
    case 2:          mode |= RADEON_AGP_2X_MODE;
    case 1: default: mode |= RADEON_AGP_1X_MODE;
    }
 
    if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-      fprintf(stderr, "[agp] AGP not enabled\n");
+      fprintf(stderr, "[gart] AGP not enabled\n");
       drmAgpRelease(ctx->drmFD);
       return 0;
    }
     
-   info->agpOffset = 0;
+   info->gartOffset = 0;
 
-   if ((ret = drmAgpAlloc(ctx->drmFD, info->agpSize*1024*1024, 0, NULL,
-			  &info->agpMemHandle)) < 0) {
-      fprintf(stderr, "[agp] Out of memory (%d)\n", ret);
+   if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
+			  &info->gartMemHandle)) < 0) {
+      fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
       drmAgpRelease(ctx->drmFD);
       return 0;
    }
    fprintf(stderr,
-	   "[agp] %d kB allocated with handle 0x%08x\n",
-	   info->agpSize*1024, (unsigned)info->agpMemHandle);
+	   "[gart] %d kB allocated with handle 0x%08x\n",
+	   info->gartSize*1024, (unsigned)info->gartMemHandle);
     
    if (drmAgpBind(ctx->drmFD,
-		  info->agpMemHandle, info->agpOffset) < 0) {
-      fprintf(stderr, "[agp] Could not bind\n");
-      drmAgpFree(ctx->drmFD, info->agpMemHandle);
+		  info->gartMemHandle, info->gartOffset) < 0) {
+      fprintf(stderr, "[gart] Could not bind\n");
+      drmAgpFree(ctx->drmFD, info->gartMemHandle);
       drmAgpRelease(ctx->drmFD);
       return 0;
    }
 
    /* Initialize the CP ring buffer data */
-   info->ringStart       = info->agpOffset;
+   info->ringStart       = info->gartOffset;
    info->ringMapSize     = info->ringSize*1024*1024 + DRM_PAGE_SIZE;
 
    info->ringReadOffset  = info->ringStart + info->ringMapSize;
@@ -378,51 +378,51 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
    info->bufMapSize      = info->bufSize*1024*1024;
 
    /* Reserve the rest for AGP textures */
-   info->agpTexStart     = info->bufStart + info->bufMapSize;
-   s = (info->agpSize*1024*1024 - info->agpTexStart);
+   info->gartTexStart     = info->bufStart + info->bufMapSize;
+   s = (info->gartSize*1024*1024 - info->gartTexStart);
    l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
    if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-   info->agpTexMapSize   = (s >> l) << l;
-   info->log2AGPTexGran  = l;
+   info->gartTexMapSize   = (s >> l) << l;
+   info->log2GARTTexGran  = l;
 
    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
 		 DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
-      fprintf(stderr, "[agp] Could not add ring mapping\n");
+      fprintf(stderr, "[gart] Could not add ring mapping\n");
       return 0;
    }
-   fprintf(stderr, "[agp] ring handle = 0x%08lx\n", info->ringHandle);
+   fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle);
     
 
    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
 		 DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
       fprintf(stderr,
-	      "[agp] Could not add ring read ptr mapping\n");
+	      "[gart] Could not add ring read ptr mapping\n");
       return 0;
    }
     
    fprintf(stderr,
-	   "[agp] ring read ptr handle = 0x%08lx\n",
+	   "[gart] ring read ptr handle = 0x%08lx\n",
 	   info->ringReadPtrHandle);
     
    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
 		 DRM_AGP, 0, &info->bufHandle) < 0) {
       fprintf(stderr,
-	      "[agp] Could not add vertex/indirect buffers mapping\n");
+	      "[gart] Could not add vertex/indirect buffers mapping\n");
       return 0;
    }
    fprintf(stderr,
-	   "[agp] vertex/indirect buffers handle = 0x%08lx\n",
+	   "[gart] vertex/indirect buffers handle = 0x%08lx\n",
 	   info->bufHandle);
 
-   if (drmAddMap(ctx->drmFD, info->agpTexStart, info->agpTexMapSize,
-		 DRM_AGP, 0, &info->agpTexHandle) < 0) {
+   if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
+		 DRM_AGP, 0, &info->gartTexHandle) < 0) {
       fprintf(stderr,
-	      "[agp] Could not add AGP texture map mapping\n");
+	      "[gart] Could not add AGP texture map mapping\n");
       return 0;
    }
    fprintf(stderr,
-	   "[agp] AGP texture map handle = 0x%08lx\n",
-	   info->agpTexHandle);
+	   "[gart] AGP texture map handle = 0x%08lx\n",
+	   info->gartTexHandle);
 
    /* Initialize Radeon's AGP registers */
    /* Ring buffer is at AGP offset 0 */
@@ -463,7 +463,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
    drmInfo.sarea_priv_offset   = sizeof(XF86DRISAREARec);
    drmInfo.is_pci              = 0;
    drmInfo.cp_mode             = RADEON_DEFAULT_CP_BM_MODE;
-   drmInfo.agp_size            = info->agpSize*1024*1024;
+   drmInfo.gart_size            = info->gartSize*1024*1024;
    drmInfo.ring_size           = info->ringSize*1024*1024;
    drmInfo.usec_timeout        = 1000;
    drmInfo.fb_bpp              = ctx->bpp;
@@ -479,7 +479,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
    drmInfo.ring_offset         = info->ringHandle;
    drmInfo.ring_rptr_offset    = info->ringReadPtrHandle;
    drmInfo.buffers_offset      = info->bufHandle;
-   drmInfo.agp_textures_offset = info->agpTexHandle;
+   drmInfo.gart_textures_offset = info->gartTexHandle;
 
    ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo, 
 			 sizeof(drmRadeonInit));
@@ -502,19 +502,19 @@ static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
 {
    drmRadeonMemInitHeap drmHeap;
 
-   /* Start up the simple memory manager for agp space */
-   drmHeap.region = RADEON_MEM_REGION_AGP;
+   /* Start up the simple memory manager for gart space */
+   drmHeap.region = RADEON_MEM_REGION_GART;
    drmHeap.start  = 0;
-   drmHeap.size   = info->agpTexMapSize;
+   drmHeap.size   = info->gartTexMapSize;
     
    if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP,
 		       &drmHeap, sizeof(drmHeap))) {
       fprintf(stderr,
-	      "[drm] Failed to initialized agp heap manager\n");
+	      "[drm] Failed to initialized gart heap manager\n");
    } else {
       fprintf(stderr,
-	      "[drm] Initialized kernel agp heap manager, %d\n",
-	      info->agpTexMapSize);
+	      "[drm] Initialized kernel gart heap manager, %d\n",
+	      info->gartTexMapSize);
    }
 }
 
@@ -640,13 +640,13 @@ static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
    info->frontPitch = ctx->shared.virtualWidth;
 
    fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", info->agpSize);
+	   "Using %d MB AGP aperture\n", info->gartSize);
    fprintf(stderr, 
 	   "Using %d MB for the ring buffer\n", info->ringSize);
    fprintf(stderr, 
 	   "Using %d MB for vertex/indirect buffers\n", info->bufSize);
    fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", info->agpTexSize);
+	   "Using %d MB for AGP textures\n", info->gartTexSize);
 
    /* Front, back and depth buffers - everything else texture??
     */
@@ -733,7 +733,7 @@ static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
  * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
  * initialization.
  */
-static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
+static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
 {
    RADEONDRIPtr   pRADEONDRI;
    int err;
@@ -883,7 +883,7 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
    /* Initialize IRQ */
    RADEONDRIIrqInit(ctx, info);
 
-   /* Initialize kernel agp memory manager */
+   /* Initialize kernel gart memory manager */
    RADEONDRIAgpHeapInit(ctx, info);
 
    /* Initialize the SAREA private data structure */
@@ -919,7 +919,7 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
    pRADEONDRI->depth             = ctx->bpp; /* XXX: depth */
    pRADEONDRI->bpp               = ctx->bpp;
    pRADEONDRI->IsPCI             = 0;
-   pRADEONDRI->AGPMode           = info->agpMode;
+   pRADEONDRI->AGPMode           = info->gartMode;
    pRADEONDRI->frontOffset       = info->frontOffset;
    pRADEONDRI->frontPitch        = info->frontPitch;
    pRADEONDRI->backOffset        = info->backOffset;
@@ -933,10 +933,10 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
    pRADEONDRI->registerSize      = info->registerSize; 
    pRADEONDRI->statusHandle      = info->ringReadPtrHandle;
    pRADEONDRI->statusSize        = info->ringReadMapSize;
-   pRADEONDRI->agpTexHandle      = info->agpTexHandle;
-   pRADEONDRI->agpTexMapSize     = info->agpTexMapSize;
-   pRADEONDRI->log2AGPTexGran    = info->log2AGPTexGran;
-   pRADEONDRI->agpTexOffset      = info->agpTexStart;
+   pRADEONDRI->gartTexHandle      = info->gartTexHandle;
+   pRADEONDRI->gartTexMapSize     = info->gartTexMapSize;
+   pRADEONDRI->log2GARTTexGran    = info->log2GARTTexGran;
+   pRADEONDRI->gartTexOffset      = info->gartTexStart;
    pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
 
    /* Don't release the lock now - let the VT switch handler do it. */
@@ -1139,10 +1139,10 @@ static int radeonInitFBDev( DRIDriverContext *ctx )
 
    ctx->driverPrivate = (void *)info;
    
-   info->agpFastWrite  = RADEON_DEFAULT_AGP_FAST_WRITE;
-   info->agpMode       = RADEON_DEFAULT_AGP_MODE;
-   info->agpSize       = RADEON_DEFAULT_AGP_SIZE;
-   info->agpTexSize    = RADEON_DEFAULT_AGP_TEX_SIZE;
+   info->gartFastWrite  = RADEON_DEFAULT_AGP_FAST_WRITE;
+   info->gartMode       = RADEON_DEFAULT_AGP_MODE;
+   info->gartSize       = RADEON_DEFAULT_AGP_SIZE;
+   info->gartTexSize    = RADEON_DEFAULT_AGP_TEX_SIZE;
    info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
    info->ringSize      = RADEON_DEFAULT_RING_SIZE;
   
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.h b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
index fce21227cb9..fc96deb1024 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
@@ -102,10 +102,10 @@ typedef struct {
      * \name CP AGP Texture data
      */
     /*@{*/
-    drmHandle     agpTexHandle;   /**< \brief AGP texture area map handle */
-    drmSize       agpTexMapSize;  /**< \brief AGP texture area map size */
-    int           log2AGPTexGran; /**< \brief AGP texture granularity in log base 2 */
-    int           agpTexOffset;   /**< \brief AGP texture area offset in AGP space */
+    drmHandle     gartTexHandle;   /**< \brief AGP texture area map handle */
+    drmSize       gartTexMapSize;  /**< \brief AGP texture area map size */
+    int           log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */
+    int           gartTexOffset;   /**< \brief AGP texture area offset in AGP space */
     /*@}*/
 
     unsigned int  sarea_priv_offset; /**< \brief offset of the private SAREA data*/
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
index 5570a439458..4bd4d14e783 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.25 2003/02/07 18:08:59 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */
 /*
  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  *                VA Linux Systems Inc., Fremont, California.
@@ -66,6 +66,8 @@
 #       define RADEON_AGP_APER_SIZE_4MB     (0x3f << 0)
 #       define RADEON_AGP_APER_SIZE_MASK    (0x3f << 0)
 #define RADEON_AGP_COMMAND                  0x0f60 /* PCI */
+#define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/
+#       define RADEON_AGP_ENABLE            (1<<8)
 #define RADEON_AGP_PLL_CNTL                 0x000b /* PLL */
 #define RADEON_AGP_STATUS                   0x0f5c /* PCI */
 #       define RADEON_AGP_1X_MODE           0x01
@@ -232,6 +234,28 @@
 #       define RADEON_CONSTANT_COLOR_ZERO   0x00000000
 #define RADEON_CRC_CMDFIFO_ADDR             0x0740
 #define RADEON_CRC_CMDFIFO_DOUT             0x0744
+#define RADEON_GRPH_BUFFER_CNTL             0x02f0
+#       define RADEON_GRPH_START_REQ_MASK          (0x7f)
+#       define RADEON_GRPH_START_REQ_SHIFT         0
+#       define RADEON_GRPH_STOP_REQ_MASK           (0x7f<<8)
+#       define RADEON_GRPH_STOP_REQ_SHIFT          8
+#       define RADEON_GRPH_CRITICAL_POINT_MASK     (0x7f<<16)
+#       define RADEON_GRPH_CRITICAL_POINT_SHIFT    16
+#       define RADEON_GRPH_CRITICAL_CNTL           (1<<28)
+#       define RADEON_GRPH_BUFFER_SIZE             (1<<29)
+#       define RADEON_GRPH_CRITICAL_AT_SOF         (1<<30)
+#       define RADEON_GRPH_STOP_CNTL               (1<<31)
+#define RADEON_GRPH2_BUFFER_CNTL            0x03f0
+#       define RADEON_GRPH2_START_REQ_MASK         (0x7f)
+#       define RADEON_GRPH2_START_REQ_SHIFT         0
+#       define RADEON_GRPH2_STOP_REQ_MASK          (0x7f<<8)
+#       define RADEON_GRPH2_STOP_REQ_SHIFT         8
+#       define RADEON_GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)
+#       define RADEON_GRPH2_CRITICAL_POINT_SHIFT   16
+#       define RADEON_GRPH2_CRITICAL_CNTL          (1<<28)
+#       define RADEON_GRPH2_BUFFER_SIZE            (1<<29)
+#       define RADEON_GRPH2_CRITICAL_AT_SOF        (1<<30)
+#       define RADEON_GRPH2_STOP_CNTL              (1<<31)
 #define RADEON_CRTC_CRNT_FRAME              0x0214
 #define RADEON_CRTC_EXT_CNTL                0x0054
 #       define RADEON_CRTC_VGA_XOVERSCAN    (1 <<  0)
@@ -272,6 +296,9 @@
 #       define RADEON_CRTC2_CSYNC_EN        (1 << 27)
 #       define RADEON_CRTC2_HSYNC_DIS       (1 << 28)
 #       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)
+#define RADEON_CRTC_MORE_CNTL               0x27c
+#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)   
+#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)   
 #define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
 #define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
 #       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
@@ -356,7 +383,10 @@
 
 #define RADEON_DAC_CNTL                     0x0058
 #       define RADEON_DAC_RANGE_CNTL        (3 <<  0)
+#       define RADEON_DAC_RANGE_CNTL_MASK   0x03
 #       define RADEON_DAC_BLANKING          (1 <<  2)
+#       define RADEON_DAC_CMP_EN            (1 <<  3)
+#       define RADEON_DAC_CMP_OUTPUT        (1 <<  7)
 #       define RADEON_DAC_8BIT_EN           (1 <<  8)
 #       define RADEON_DAC_VGA_ADR_EN        (1 << 13)
 #       define RADEON_DAC_PDWN              (1 << 15)
@@ -365,6 +395,12 @@
 #       define RADEON_DAC2_DAC_CLK_SEL      (1 <<  0)
 #       define RADEON_DAC2_DAC2_CLK_SEL     (1 <<  1)
 #       define RADEON_DAC2_PALETTE_ACC_CTL  (1 <<  5)
+#define RADEON_DAC_EXT_CNTL                 0x0280
+#       define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
+#       define RADEON_DAC_FORCE_DATA_EN      (1 << 5)
+#       define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
+#       define RADEON_DAC_FORCE_DATA_MASK   0x0003ff00
+#       define RADEON_DAC_FORCE_DATA_SHIFT  8
 #define RADEON_TV_DAC_CNTL                  0x088c
 #       define RADEON_TV_DAC_STD_MASK       0x0300
 #       define RADEON_TV_DAC_RDACPD         (1 <<  24)
@@ -374,7 +410,9 @@
 #       define RADEON_CRT2_DISP1_SEL        (1 <<  5)
 #define RADEON_DISP_OUTPUT_CNTL             0x0d64
 #       define RADEON_DISP_DAC_SOURCE_MASK  0x03
+#       define RADEON_DISP_DAC2_SOURCE_MASK  0x0c
 #       define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
+#       define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
 #define RADEON_DAC_CRC_SIG                  0x02cc
 #define RADEON_DAC_DATA                     0x03c9 /* VGA */
 #define RADEON_DAC_MASK                     0x03c6 /* VGA */
@@ -392,6 +430,23 @@
 #define RADEON_DEVICE_ID                    0x0f02 /* PCI */
 #define RADEON_DISP_MISC_CNTL               0x0d00
 #       define RADEON_SOFT_RESET_GRPH_PP    (1 << 0)
+#define RADEON_DISP_MERGE_CNTL	          0x0d60
+#       define RADEON_DISP_ALPHA_MODE_MASK  0x03
+#       define RADEON_DISP_ALPHA_MODE_KEY   0
+#       define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
+#       define RADEON_DISP_ALPHA_MODE_GLOBAL 2
+#       define RADEON_DISP_RGB_OFFSET_EN    (1<<8)
+#       define RADEON_DISP_GRPH_ALPHA_MASK  (0xff << 16)
+#       define RADEON_DISP_OV0_ALPHA_MASK   (0xff << 24)
+#	define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
+#define RADEON_DISP2_MERGE_CNTL	            0x0d68
+#       define RADEON_DISP2_RGB_OFFSET_EN   (1<<8)
+#define RADEON_DISP_LIN_TRANS_GRPH_A        0x0d80
+#define RADEON_DISP_LIN_TRANS_GRPH_B        0x0d84
+#define RADEON_DISP_LIN_TRANS_GRPH_C        0x0d88
+#define RADEON_DISP_LIN_TRANS_GRPH_D        0x0d8c
+#define RADEON_DISP_LIN_TRANS_GRPH_E        0x0d90
+#define RADEON_DISP_LIN_TRANS_GRPH_F        0x0d98
 #define RADEON_DP_BRUSH_BKGD_CLR            0x1478
 #define RADEON_DP_BRUSH_FRGD_CLR            0x147c
 #define RADEON_DP_CNTL                      0x16c0
@@ -582,7 +637,10 @@
 #       define RADEON_FP2_BLANK_EN             (1 <<  1)
 #       define RADEON_FP2_ON                   (1 <<  2)
 #       define RADEON_FP2_PANEL_FORMAT         (1 <<  3)
-#       define RADEON_FP2_SEL_CRTC2            (1 << 13)
+#       define RADEON_FP2_SOURCE_SEL_MASK      (3 << 10)
+#       define RADEON_FP2_SOURCE_SEL_CRTC2     (1 << 10)
+#       define RADEON_FP2_SRC_SEL_MASK         (3 << 13)
+#       define RADEON_FP2_SRC_SEL_CRTC2        (1 << 13)
 #       define RADEON_FP2_FP_POL               (1 << 16)
 #       define RADEON_FP2_LP_POL               (1 << 17)
 #       define RADEON_FP2_SCK_POL              (1 << 18)
@@ -590,6 +648,8 @@
 #       define RADEON_FP2_PAD_FLOP_EN          (1 << 22)
 #       define RADEON_FP2_CRC_EN               (1 << 23)
 #       define RADEON_FP2_CRC_READ_EN          (1 << 24)
+#       define RADEON_FP2_DV0_EN               (1 << 25)
+#       define RADEON_FP2_DV0_RATE_SEL_SDR     (1 << 26)
 #define RADEON_FP_H_SYNC_STRT_WID           0x02c4
 #define RADEON_FP_H2_SYNC_STRT_WID          0x03c4
 #define RADEON_FP_HORZ_STRETCH              0x028c
@@ -697,6 +757,10 @@
 #define RADEON_MAX_LATENCY                  0x0f3f /* PCI */
 #define RADEON_MC_AGP_LOCATION              0x014c
 #define RADEON_MC_FB_LOCATION               0x0148
+#define RADEON_DISPLAY_BASE_ADDR            0x23c
+#define RADEON_DISPLAY2_BASE_ADDR           0x33c
+#define RADEON_OV0_BASE_ADDR                0x43c
+#define RADEON_NB_TOM                       0x15c
 #define RADEON_MCLK_CNTL                    0x0012 /* PLL */
 #       define RADEON_FORCEON_MCLKA         (1 << 16)
 #       define RADEON_FORCEON_MCLKB         (1 << 17)
@@ -711,6 +775,12 @@
 #define RADEON_MEM_ADDR_CONFIG              0x0148
 #define RADEON_MEM_BASE                     0x0f10 /* PCI */
 #define RADEON_MEM_CNTL                     0x0140
+#       define RADEON_MEM_NUM_CHANNELS_MASK 0x01
+#       define RADEON_MEM_USE_B_CH_ONLY     (1<<1)
+#       define RV100_HALF_MODE              (1<<3)
+#       define R300_MEM_NUM_CHANNELS_MASK   0x03
+#       define R300_MEM_USE_CD_CH_ONLY      (1<<2)
+#define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
 #define RADEON_MEM_INIT_LAT_TIMER           0x0154
 #define RADEON_MEM_INTF_CNTL                0x014c
 #define RADEON_MEM_SDRAM_MODE_REG           0x0158
@@ -723,7 +793,13 @@
 #define RADEON_MPLL_CNTL                    0x000e /* PLL */
 #define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */
 #define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */
-
+#define R300_MC_IND_INDEX                   0x01f8
+#       define R300_MC_IND_ADDR_MASK        0x3f
+#define R300_MC_IND_DATA                    0x01fc
+#define R300_MC_READ_CNTL_AB                0x017c
+#       define R300_MEM_RBS_POSITION_A_MASK 0x03
+#define R300_MC_READ_CNTL_CD_mcind	    0x24
+#       define R300_MEM_RBS_POSITION_C_MASK 0x03
 
 #define RADEON_N_VIF_COUNT                  0x0248
 
@@ -879,7 +955,7 @@
 #       define RADEON_P2PLL_REF_DIV_MASK    0x03ff
 #       define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
 #       define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#       define R300_PPLL_REF_DIV_ACC_MASK   (0x3ff < 18)
+#       define R300_PPLL_REF_DIV_ACC_MASK   (0x3ff << 18)
 #       define R300_PPLL_REF_DIV_ACC_SHIFT  18
 #define RADEON_PALETTE_DATA                 0x00b4
 #define RADEON_PALETTE_30_DATA              0x00b8
@@ -891,6 +967,11 @@
 #       define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
 #       define RADEON_PIX2CLK_SRC_SEL_BYTECLK  0x02
 #       define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
+#       define RADEON_PIX2CLK_ALWAYS_ONb       (1<<6)
+#       define RADEON_PIX2CLK_DAC_ALWAYS_ONb   (1<<7)
+#       define RADEON_PIXCLK_TV_SRC_SEL        (1 << 8)
+#       define RADEON_PIXCLK_LVDS_ALWAYS_ONb   (1 << 14)
+#       define RADEON_PIXCLK_TMDS_ALWAYS_ONb   (1 << 15)
 #define RADEON_PLANE_3D_MASK_C              0x1d44
 #define RADEON_PLL_TEST_CNTL                0x0013 /* PLL */
 #define RADEON_PMI_CAP_ID                   0x0f5c /* PCI */
@@ -1013,6 +1094,9 @@
 #define RADEON_TEST_DEBUG_MUX               0x0124
 #define RADEON_TEST_DEBUG_OUT               0x012c
 #define RADEON_TMDS_PLL_CNTL                0x02a8
+#define RADEON_TMDS_TRANSMITTER_CNTL        0x02a4
+#       define RADEON_TMDS_TRANSMITTER_PLLEN  1
+#       define RADEON_TMDS_TRANSMITTER_PLLRST 2
 #define RADEON_TRAIL_BRES_DEC               0x1614
 #define RADEON_TRAIL_BRES_ERR               0x160c
 #define RADEON_TRAIL_BRES_INC               0x1610
@@ -1025,6 +1109,9 @@
 #       define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
 #       define RADEON_VCLK_SRC_SEL_BYTECLK  0x02
 #       define RADEON_VCLK_SRC_SEL_PPLLCLK  0x03
+#       define RADEON_PIXCLK_ALWAYS_ONb     (1<<6)
+#       define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
+
 #define RADEON_VENDOR_ID                    0x0f00 /* PCI */
 #define RADEON_VGA_DDA_CONFIG               0x02e8
 #define RADEON_VGA_DDA_ON_OFF               0x02ec
@@ -1878,12 +1965,11 @@
 
 #define RADEON_AIC_CNTL                     0x01d0
 #       define RADEON_PCIGART_TRANSLATE_EN     (1 << 0)
+#define RADEON_AIC_LO_ADDR                  0x01dc
 
 
 
 				/* Constants */
-#define RADEON_AGP_TEX_OFFSET               0x02000000
-
 #define RADEON_LAST_FRAME_REG               RADEON_GUI_SCRATCH_REG0
 #define RADEON_LAST_CLEAR_REG               RADEON_GUI_SCRATCH_REG2
 
@@ -2012,4 +2098,16 @@
 #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR    51
 #define RADEON_SS_SHININESS                      60
 
+#define RADEON_TV_MASTER_CNTL                    0x0800
+#       define RADEON_TVCLK_ALWAYS_ONb           (1 << 30)
+#define RADEON_TV_DAC_CNTL                       0x088c
+#       define RADEON_TV_DAC_CMPOUT              (1 << 5)
+#define RADEON_TV_PRE_DAC_MUX_CNTL               0x0888
+#       define RADEON_Y_RED_EN                   (1 << 0)
+#       define RADEON_C_GRN_EN                   (1 << 1)
+#       define RADEON_CMP_BLU_EN                 (1 << 2)
+#       define RADEON_RED_MX_FORCE_DAC_DATA      (6 << 4)
+#       define RADEON_GRN_MX_FORCE_DAC_DATA      (6 << 8)
+#       define RADEON_BLU_MX_FORCE_DAC_DATA      (6 << 12)
+#       define RADEON_TV_FORCE_DAC_DATA_SHIFT    16
 #endif
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_sarea.h b/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
index 81e4325d7a1..95db1f37ac9 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
@@ -1,11 +1,4 @@
-/**
- * \file server/radeon_sarea.h
- * \brief SAREA definition.
- * 
- * \author Kevin E. Martin <[email protected]>
- * \author Gareth Hughes <[email protected]>
- */
-
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.5 2002/10/30 12:52:14 alanh Exp $ */
 /*
  * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
  *                VA Linux Systems Inc., Fremont, California.
@@ -34,7 +27,12 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.4 2002/04/24 16:20:41 martin Exp $ */
+/*
+ * Authors:
+ *   Kevin E. Martin <[email protected]>
+ *   Gareth Hughes <[email protected]>
+ *
+ */
 
 #ifndef _RADEON_SAREA_H_
 #define _RADEON_SAREA_H_
@@ -94,11 +92,11 @@
 /* Keep these small for testing */
 #define RADEON_NR_SAREA_CLIPRECTS	12
 
-/* There are 2 heaps (local/AGP).  Each region within a heap is a
+/* There are 2 heaps (local/GART).  Each region within a heap is a
  * minimum of 64k, and there are at most 64 of them per heap.
  */
 #define RADEON_CARD_HEAP		0
-#define RADEON_AGP_HEAP			1
+#define RADEON_GART_HEAP		1
 #define RADEON_NR_TEX_HEAPS		2
 #define RADEON_NR_TEX_REGIONS		64
 #define RADEON_LOG_TEX_GRANULARITY	16
@@ -115,10 +113,6 @@
 
 #endif /* __RADEON_SAREA_DEFINES__ */
 
-
-/**
- * \brief Color register format.
- */
 typedef struct {
     unsigned int red;
     unsigned int green;
@@ -126,15 +120,8 @@ typedef struct {
     unsigned int alpha;
 } radeon_color_regs_t;
 
-
-/**
- * \brief Context registers.
- */
 typedef struct {
-    /**
-     * \name Context state
-     */
-    /*@{*/
+    /* Context state */
     unsigned int pp_misc;
     unsigned int pp_fog_color;
     unsigned int re_solid_color;
@@ -149,76 +136,44 @@ typedef struct {
     unsigned int re_width_height;
     unsigned int rb3d_colorpitch;
     unsigned int se_cntl;
-    /*@}*/
 
-    /**
-     * \name Vertex format state
-     */
-    /*@{*/
+    /* Vertex format state */
     unsigned int se_coord_fmt;
-    /*@}*/
 
-    /**
-     * \name Line state
-     */
-    /*@{*/
+    /* Line state */
     unsigned int re_line_pattern;
     unsigned int re_line_state;
 
     unsigned int se_line_width;
-    /*@}*/
 
-    /**
-     * \name Bumpmap state
-     */
-    /*@{*/
+    /* Bumpmap state */
     unsigned int pp_lum_matrix;
 
     unsigned int pp_rot_matrix_0;
     unsigned int pp_rot_matrix_1;
-    /*@}*/
 
-    /**
-     * \name Mask state
-     */
-    /*@{*/
+    /* Mask state */
     unsigned int rb3d_stencilrefmask;
     unsigned int rb3d_ropcntl;
     unsigned int rb3d_planemask;
-    /*@}*/
 
-    /** 
-     * \name Viewport state
-     */
-    /*@{*/
+    /* Viewport state */
     unsigned int se_vport_xscale;
     unsigned int se_vport_xoffset;
     unsigned int se_vport_yscale;
     unsigned int se_vport_yoffset;
     unsigned int se_vport_zscale;
     unsigned int se_vport_zoffset;
-    /*@}*/
 
-    /**
-     * \name Setup state
-     */
-    /*@{*/
+    /* Setup state */
     unsigned int se_cntl_status;
-    /*@}*/
 
-    /** 
-     * \name Misc state
-     */
-    /*@{*/
+    /* Misc state */
     unsigned int re_top_left;
     unsigned int re_misc;
-    /*@}*/
 } radeon_context_regs_t;
 
-
-/**
- * \brief Setup registers for each texture unit
- */
+/* Setup registers for each texture unit */
 typedef struct {
     unsigned int pp_txfilter;
     unsigned int pp_txformat;
@@ -229,82 +184,48 @@ typedef struct {
     unsigned int pp_border_color;
 } radeon_texture_regs_t;
 
-/**
- * \brief Maintain an LRU of contiguous regions of texture space.  
- *
- * If you think you own a region of texture memory, and it has an age different
- * to the one you set, then you are mistaken and it has been stolen by another
- * client.  If global RADEONSAREAPriv::texAge hasn't changed, there is no need to walk the list.
- *
- * These regions can be used as a proxy for the fine-grained texture
- * information of other clients - by maintaining them in the same LRU which is
- * used to age their own textures, clients have an approximate LRU for the
- * whole of global texture space, and can make informed decisions as to which
- * areas to kick out.  There is no need to choose whether to kick out your own
- * texture or someone else's - simply eject them all in LRU order.
- * 
- * \sa RADEONSAREAPriv::texList.
- */
-typedef struct {
-    unsigned char next; 	/**< \brief indices to form a circular LRU */
-    unsigned char prev;		/**< \brief indices to form a circular LRU */
-    unsigned char in_use;	/**< \brief owned by a client, or free? */
-    int age;			/**< \brief tracked by clients to update local LRU's */
-} radeon_tex_region_t;
-
-
-/**
- * \brief Private SAREA definition
- *
- * The channel for communication of state information to the kernel
- * on firing a vertex buffer.
- */
 typedef struct {
-    radeon_context_regs_t ContextState; /** \brief Context registers */
+    /* The channel for communication of state information to the kernel
+     * on firing a vertex buffer.
+     */
+    radeon_context_regs_t ContextState;
     radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
-                                        /**< \brief Texture registers */
-    unsigned int dirty; 
-    unsigned int vertsize;              /**< \brief vertex size */
-    unsigned int vc_format;             /**< \brief vertex format */
+    unsigned int dirty;
+    unsigned int vertsize;
+    unsigned int vc_format;
 
-    /**
-     * \name Cliprects 
-     *
-     * The current cliprects, or a subset thereof.
-     */
-    /*@{*/
-    XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS]; 
-                       /**< \brief cliprects */
-    unsigned int nbox; /**< \brief number of cliprects */
-    /*@}*/
-
-    /**
-     * \name Counters
-     *
-     * Counters for throttling rendering of clients.
-     */
-    /*@{*/
-    unsigned int last_frame;    /**< \brief last emmited frame */
+    /* The current cliprects, or a subset thereof */
+    XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
+    unsigned int nbox;
+
+    /* Counters for throttling of rendering clients */
+    unsigned int last_frame;
     unsigned int last_dispatch;
-    unsigned int last_clear;    /**< \brief last emmited clear */
-    /*@}*/
+    unsigned int last_clear;
 
-    /**
-     * \name LRU
-     */
-    /*@{*/
-    /** \brief Texture regions. 
-     * Last element is sentinal
+    /* Maintain an LRU of contiguous regions of texture space.  If you
+     * think you own a region of texture memory, and it has an age
+     * different to the one you set, then you are mistaken and it has
+     * been stolen by another client.  If global texAge hasn't changed,
+     * there is no need to walk the list.
+     *
+     * These regions can be used as a proxy for the fine-grained texture
+     * information of other clients - by maintaining them in the same
+     * lru which is used to age their own textures, clients have an
+     * approximate lru for the whole of global texture space, and can
+     * make informed decisions as to which areas to kick out.  There is
+     * no need to choose whether to kick out your own texture or someone
+     * else's - simply eject them all in LRU order.
      */
+				/* Last elt is sentinal */
     drmTextureRegion texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
-    /** \brief last time texture was uploaded */
+				/* last time texture was uploaded */
     unsigned int texAge[RADEON_NR_TEX_HEAPS];
-    /*@}*/
 
-    int ctxOwner;		/**< \brief last context to upload state */
-    int pfAllowPageFlip;	/**< \brief set by the 2d driver, read by the client */
-    int pfCurrentPage;		/**< \brief set by kernel, read by others */
-    int crtc2_base;		/**< \brief for pageflipping with CloneMode */
+    int ctxOwner;		/* last context to upload state */
+    int pfAllowPageFlip;	/* set by the 2d driver, read by the client */
+    int pfCurrentPage;		/* set by kernel, read by others */
+    int crtc2_base;		/* for pageflipping with CloneMode */
 } RADEONSAREAPriv, *RADEONSAREAPrivPtr;
 
 #endif
author	Jon Smirl <[email protected]>	2003-10-21 06:05:39 +0000
committer	Jon Smirl <[email protected]>	2003-10-21 06:05:39 +0000
commit	bcc6eddd335e97d49ed2ef3a1440f94d58dce12d (patch)
tree	ff4883dd4da6ce65500940aebe2c268716311fe6 /src/mesa/drivers/dri/radeon
parent	906449753f126f74ad3321d0af897f6609880c17 (diff)