diff options
| author | Xiang, Haihao <[email protected]> | 2008-08-05 11:28:54 +0800 |
|---|---|---|
| committer | Xiang, Haihao <[email protected]> | 2008-08-05 11:34:26 +0800 |
| commit | 8e8019b49ab137403ba92aef3e286f4e27049ad5 (patch) | |
| tree | 2bd99df8f04c891a4da08c8fd971fb95598eae51 /src/mesa/drivers/dri/radeon | |
| parent | a3024caff1c790cf9f24476926aa62198f1e7b53 (diff) | |
dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_span.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 732a85ecf0b..e7ab3677b36 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -173,6 +173,8 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) /* 16-bit depth buffer functions */ +#define VALUE_TYPE GLushort + #define WRITE_DEPTH( _x, _y, d ) \ *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d; @@ -187,6 +189,8 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) * Careful: It looks like the R300 uses ZZZS byte order while the R200 * uses SZZZ for 24 bit depth, 8 bit stencil mode. */ +#define VALUE_TYPE GLuint + #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ |