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authorMario Kleiner <[email protected]>2010-08-02 04:17:03 +0200
committerJerome Glisse <[email protected]>2010-08-02 13:29:44 -0400
commit646d2e9fbc41bf49075013009e9583bec4a51168 (patch)
treee85b296ce4e1736cda0282d82f0297e9b06ab77e /src/mesa/drivers/dri/radeon/radeon_tcl.c
parent3d39f56a8721ec6aa6d00965b7740fc8cb5edaae (diff)
radeon: Add DRI2 flush extension support, so we synchronize properly.
When a DRI2 swap buffer is pending we need to make sure we have the flush extension so radeon doesn't resume rendering to or reading from the not yet blitted front buffer. This fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28341 https://bugs.freedesktop.org/show_bug.cgi?id=28410 Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Mario Kleiner <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_tcl.c')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tcl.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index ea796e1a45f..5e1718f9dfc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -252,6 +252,8 @@ void radeonTclPrimitive( GLcontext *ctx,
GLuint se_cntl;
GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
+ radeon_prepare_render(&rmesa->radeon);
+
if (newprim != rmesa->tcl.hw_primitive ||
!discrete_prim[hw_prim&0xf]) {
RADEON_NEWPRIM( rmesa );