diff options
| author | Roland Scheidegger <[email protected]> | 2007-11-22 02:49:11 +0100 |
|---|---|---|
| committer | Roland Scheidegger <[email protected]> | 2007-11-22 02:49:15 +0100 |
| commit | 3d51c7900105a99fc30a4318080fd4cc373c8eec (patch) | |
| tree | 4edb0bb3bdb96286e2f9de90243cbe4d8db7c12e /src/mesa/drivers/dri/radeon/radeon_screen.c | |
| parent | 93c98a466947570e0589b662df49095b2f4bc43c (diff) | |
fix z buffer read/write issue with rv100-like chips and old ddx
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_screen.c')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index c12eef20242..e9c9df12229 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -720,7 +720,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthPitch = dri_priv->depthPitch; /* Check if ddx has set up a surface reg to cover depth buffer */ - screen->depthHasSurface = (sPriv->ddx_version.major > 4); + screen->depthHasSurface = (sPriv->ddx_version.major > 4) || + /* these chips don't use tiled z without hyperz. So always pretend + we have set up a surface which will cause linear reads/writes */ + ((screen->chip_family & RADEON_CLASS_R100) && + !(screen->chip_flags & RADEON_CHIPSET_TCL)); if ( dri_priv->textureSize == 0 ) { screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; |