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authorAlex Deucher <[email protected]>2009-09-14 18:05:15 -0400
committerAlex Deucher <[email protected]>2009-09-14 18:10:24 -0400
commit364ca57aff733e8ee5f417b3f8719514f443315f (patch)
tree95b08d99b72f1afe388dbf239ce9fb03ec087664 /src/mesa/drivers/dri/r600/r700_chip.c
parentf662cedae446b124ff3f370c21cc7bb2e08244a0 (diff)
r600: add span support for 1D tiles
1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z*
Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_chip.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 1b560591974..06d7e9c9ab1 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -351,7 +351,7 @@ static void r700SetDepthTarget(context_t *context)
SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
}
- SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
+ SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
/* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
}