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authorJerome Glisse <[email protected]>2009-05-28 11:40:58 +0200
committerJerome Glisse <[email protected]>2009-05-28 11:40:58 +0200
commit2f9189d538ac56bd241ccc8f8f82bc4fdd779aa6 (patch)
tree5f445839f3bc4ea8daabef152cf64441b1b8f485 /src/mesa/drivers/dri/r300
parent3a6dd3ebb33a35779b0d5be2c8cab581a56f245a (diff)
r300: rework texture offset emission.
Diffstat (limited to 'src/mesa/drivers/dri/r300')
-rw-r--r--src/mesa/drivers/dri/r300/r300_cmdbuf.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 60ad8ea14b3..e605076a519 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -179,27 +179,33 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
if (r300->radeon.radeonScreen->kernel_mm && notexture) {
return;
}
- BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
if (t && !t->image_override) {
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ END_BATCH();
} else if (!t) {
- OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
+ /* Texture unit hasn't a texture bound nothings to do */
} else { /* override cases */
if (t->bo) {
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ END_BATCH();
} else if (!r300->radeon.radeonScreen->kernel_mm) {
+ BEGIN_BATCH_NO_AUTOSTATE(2);
+ OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH(t->override_offset);
- }
- else
- OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
+ END_BATCH();
+ } else {
+ /* Texture unit hasn't a texture bound nothings to do */
+ }
}
}
- END_BATCH();
}
}