diff options
| author | Eric Anholt <[email protected]> | 2011-10-20 15:06:54 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2011-10-28 11:20:30 -0700 |
| commit | de22b9018f2516a3948d920c6bb1ffe659d7f230 (patch) | |
| tree | 670f04a88927f5c3bbae66054d0c926d06308d1d /src/mesa/drivers/dri/r300 | |
| parent | 2f4c7ebea683de1d84501cfd11dbb963e7c027f6 (diff) | |
r300c, r600c: Remove these DRI drivers.
They have been superseded by the gallium equivalents.
Acked-by: Michel Dänzer <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Acked-by: Dave Airlie <[email protected]>
Acked-by: Corbin Simpson <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/r300')
72 files changed, 0 insertions, 13405 deletions
diff --git a/src/mesa/drivers/dri/r300/Lindent b/src/mesa/drivers/dri/r300/Lindent deleted file mode 100755 index 7d8d8896e30..00000000000 --- a/src/mesa/drivers/dri/r300/Lindent +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@" diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile deleted file mode 100644 index 55c75802cef..00000000000 --- a/src/mesa/drivers/dri/r300/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -# src/mesa/drivers/dri/r300/Makefile - -TOP = ../../../../.. -include $(TOP)/configs/current - -LIBNAME = r300_dri.so - -include ../Makefile.defines - -ifeq ($(RADEON_LDFLAGS),) -CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c -endif - -RADEON_COMMON_SOURCES = \ - radeon_bo_legacy.c \ - radeon_buffer_objects.c \ - radeon_common_context.c \ - radeon_common.c \ - radeon_cs_legacy.c \ - radeon_dma.c \ - radeon_debug.c \ - radeon_fbo.c \ - radeon_lock.c \ - radeon_mipmap_tree.c \ - radeon_pixel_read.c \ - radeon_queryobj.c \ - radeon_span.c \ - radeon_texture.c \ - radeon_tex_copy.c \ - radeon_tile.c - -DRIVER_SOURCES = \ - radeon_screen.c \ - r300_blit.c \ - r300_context.c \ - r300_draw.c \ - r300_cmdbuf.c \ - r300_state.c \ - r300_render.c \ - r300_tex.c \ - r300_texstate.c \ - r300_vertprog.c \ - r300_fragprog_common.c \ - r300_shader.c \ - radeon_mesa_to_rc.c \ - r300_emit.c \ - r300_swtcl.c \ - $(RADEON_COMMON_SOURCES) \ - $(EGL_SOURCES) \ - $(CS_SOURCES) - -C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES) - -DRIVER_DEFINES = -DRADEON_R300 -# -DRADEON_BO_TRACK \ - -INCLUDES += $(RADEON_CFLAGS) -DRI_LIB_DEPS += $(RADEON_LDFLAGS) - -SUBDIRS = compiler - -EXTRA_MODULES = compiler/libr300compiler.a - - -##### TARGETS ##### - -include ../Makefile.targets - diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c deleted file mode 100644 index c525f0ffe2f..00000000000 --- a/src/mesa/drivers/dri/r300/r300_blit.c +++ /dev/null @@ -1,674 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "radeon_common.h" -#include "r300_context.h" - -#include "r300_blit.h" -#include "r300_cmdbuf.h" -#include "r300_emit.h" -#include "r300_tex.h" -#include "compiler/radeon_compiler.h" -#include "compiler/radeon_opcodes.h" - -static void vp_ins_outs(struct r300_vertex_program_compiler *c) -{ - c->code->inputs[VERT_ATTRIB_POS] = 0; - c->code->inputs[VERT_ATTRIB_TEX0] = 1; - c->code->outputs[VERT_RESULT_HPOS] = 0; - c->code->outputs[VERT_RESULT_TEX0] = 1; -} - -static void fp_allocate_hw_inputs( - struct r300_fragment_program_compiler * c, - void (*allocate)(void * data, unsigned input, unsigned hwreg), - void * mydata) -{ - allocate(mydata, FRAG_ATTRIB_TEX0, 0); -} - -static void create_vertex_program(struct r300_context *r300) -{ - struct r300_vertex_program_compiler compiler; - struct rc_instruction *inst; - - memset(&compiler, 0, sizeof(compiler)); - rc_init(&compiler.Base); - - inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); - inst->U.I.Opcode = RC_OPCODE_MOV; - inst->U.I.DstReg.File = RC_FILE_OUTPUT; - inst->U.I.DstReg.Index = VERT_RESULT_HPOS; - inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; - inst->U.I.SrcReg[0].Abs = 0; - inst->U.I.SrcReg[0].File = RC_FILE_INPUT; - inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS; - inst->U.I.SrcReg[0].Negate = 0; - inst->U.I.SrcReg[0].RelAddr = 0; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; - - inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); - inst->U.I.Opcode = RC_OPCODE_MOV; - inst->U.I.DstReg.File = RC_FILE_OUTPUT; - inst->U.I.DstReg.Index = VERT_RESULT_TEX0; - inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; - inst->U.I.SrcReg[0].Abs = 0; - inst->U.I.SrcReg[0].File = RC_FILE_INPUT; - inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0; - inst->U.I.SrcReg[0].Negate = 0; - inst->U.I.SrcReg[0].RelAddr = 0; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; - - compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0); - compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0); - compiler.SetHwInputOutput = vp_ins_outs; - compiler.code = &r300->blit.vp_code; - compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; - compiler.Base.disable_optimizations = 0; - compiler.Base.has_half_swizzles = 0; - compiler.Base.max_temp_regs = 32; - compiler.Base.max_constants = 256; - compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256; - - r3xx_compile_vertex_program(&compiler); -} - -static void create_fragment_program(struct r300_context *r300) -{ - struct r300_fragment_program_compiler compiler; - struct rc_instruction *inst; - - memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler)); - rc_init(&compiler.Base); - - inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev); - inst->U.I.Opcode = RC_OPCODE_TEX; - inst->U.I.TexSrcTarget = RC_TEXTURE_2D; - inst->U.I.TexSrcUnit = 0; - inst->U.I.DstReg.File = RC_FILE_OUTPUT; - inst->U.I.DstReg.Index = FRAG_RESULT_COLOR; - inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; - inst->U.I.SrcReg[0].Abs = 0; - inst->U.I.SrcReg[0].File = RC_FILE_INPUT; - inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0; - inst->U.I.SrcReg[0].Negate = 0; - inst->U.I.SrcReg[0].RelAddr = 0; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; - inst->U.I.TexSwizzle = RC_SWIZZLE_XYZW; - - compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0); - compiler.OutputColor[0] = FRAG_RESULT_COLOR; - compiler.OutputDepth = FRAG_RESULT_DEPTH; - compiler.enable_shadow_ambient = GL_TRUE; - compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515); - compiler.Base.disable_optimizations = 0; - compiler.Base.has_half_swizzles = 1; - compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32; - compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; - compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; - compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32; - compiler.code = &r300->blit.fp_code; - compiler.AllocateHwInputs = fp_allocate_hw_inputs; - - r3xx_compile_fragment_program(&compiler); -} - -void r300_blit_init(struct r300_context *r300) -{ - if (r300->options.hw_tcl_enabled) - create_vertex_program(r300); - create_fragment_program(r300); -} - -static void r300_emit_tx_setup(struct r300_context *r300, - gl_format mesa_format, - struct radeon_bo *bo, - intptr_t offset, - unsigned width, - unsigned height, - unsigned pitch) -{ - int is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; - BATCH_LOCALS(&r300->radeon); - - assert(is_r500 ? width <= 4096 : width <= 2048); - assert(is_r500 ? height <= 4096 : height <= 2048); - assert(r300TranslateTexFormat(mesa_format) >= 0); - assert(offset % 32 == 0); - - BEGIN_BATCH(17); - OUT_BATCH_REGVAL(R300_TX_FILTER0_0, - (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) | - (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) | - (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT) | - R300_TX_MIN_FILTER_MIP_NONE | - R300_TX_MIN_FILTER_NEAREST | - R300_TX_MAG_FILTER_NEAREST | - (0 << 28)); - OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0); - OUT_BATCH_REGVAL(R300_TX_SIZE_0, - (((width - 1) & 0x7ff) << R300_TX_WIDTHMASK_SHIFT) | - (((height - 1) & 0x7ff) << R300_TX_HEIGHTMASK_SHIFT) | - (0 << R300_TX_DEPTHMASK_SHIFT) | - (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) | - R300_TX_SIZE_TXPITCH_EN); - - OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format)); - OUT_BATCH_REGVAL(R300_TX_FORMAT2_0, - (pitch - 1) | - (is_r500 && width > 2048 ? R500_TXWIDTH_BIT11 : 0) | - (is_r500 && height > 2048 ? R500_TXHEIGHT_BIT11 : 0)); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1); - OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - - OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2); - OUT_BATCH(0); - OUT_BATCH(1); - - END_BATCH(); -} - -#define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \ - (FMT | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \ - R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN)) - -static uint32_t mesa_format_to_us_format(gl_format mesa_format) -{ - switch(mesa_format) - { - case MESA_FORMAT_RGBA8888: // x - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0); - case MESA_FORMAT_RGB565: // x - case MESA_FORMAT_ARGB1555: // x - case MESA_FORMAT_RGBA8888_REV: // x - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0); - case MESA_FORMAT_ARGB8888: // x - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0); - case MESA_FORMAT_ARGB8888_REV: - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0); - case MESA_FORMAT_XRGB8888: - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0); - - case MESA_FORMAT_RGB332: - return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0); - - case MESA_FORMAT_RGBA_FLOAT32: - return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0); - case MESA_FORMAT_RGBA_FLOAT16: - return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0); - case MESA_FORMAT_ALPHA_FLOAT32: - return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0); - case MESA_FORMAT_ALPHA_FLOAT16: - return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0); - - case MESA_FORMAT_SIGNED_RGBA8888: - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf); - case MESA_FORMAT_SIGNED_RGBA8888_REV: - return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf); - case MESA_FORMAT_SIGNED_RGBA_16: - return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf); - - default: - fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format)); - assert(0); - return 0; - } -} -#undef EASY_US_FORMAT - -static void r500_emit_fp_setup(struct r300_context *r300, - struct r500_fragment_program_code *fp, - gl_format dst_format) -{ - r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0); - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH(10); - OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3); - OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end)); - OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end)); - OUT_BATCH(0); - OUT_BATCH_REGVAL(R500_US_CONFIG, 0); - OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format)); - OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx); - END_BATCH(); -} - -static void r500_emit_rs_setup(struct r300_context *r300) -{ - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH(7); - OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); - OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN); - OUT_BATCH(0); - OUT_BATCH_REGVAL(R500_RS_INST_0, - (0 << R500_RS_INST_TEX_ID_SHIFT) | - (0 << R500_RS_INST_TEX_ADDR_SHIFT) | - R500_RS_INST_TEX_CN_WRITE | - R500_RS_INST_COL_CN_NO_WRITE); - OUT_BATCH_REGVAL(R500_RS_IP_0, - (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (2 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (3 << R500_RS_IP_TEX_PTR_Q_SHIFT)); - END_BATCH(); -} - -static void r300_emit_fp_setup(struct r300_context *r300, - struct r300_fragment_program_code *code, - gl_format dst_format) -{ - unsigned i; - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11); - - OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length); - for (i = 0; i < code->alu.length; i++) { - OUT_BATCH(code->alu.inst[i].rgb_inst); - } - OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length); - for (i = 0; i < code->alu.length; i++) { - OUT_BATCH(code->alu.inst[i].rgb_addr); - } - OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length); - for (i = 0; i < code->alu.length; i++) { - OUT_BATCH(code->alu.inst[i].alpha_inst); - } - OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length); - for (i = 0; i < code->alu.length; i++) { - OUT_BATCH(code->alu.inst[i].alpha_addr); - } - - OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length); - OUT_BATCH_TABLE(code->tex.inst, code->tex.length); - - OUT_BATCH_REGSEQ(R300_US_CONFIG, 3); - OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX); - OUT_BATCH(code->pixsize); - OUT_BATCH(code->code_offset); - OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4); - OUT_BATCH_TABLE(code->code_addr, 4); - OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format)); - END_BATCH(); -} - -static void r300_emit_rs_setup(struct r300_context *r300) -{ - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH(7); - OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); - OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN); - OUT_BATCH(0); - OUT_BATCH_REGVAL(R300_RS_INST_0, - R300_RS_INST_TEX_ID(0) | - R300_RS_INST_TEX_ADDR(0) | - R300_RS_INST_TEX_CN_WRITE); - OUT_BATCH_REGVAL(R300_RS_IP_0, - R300_RS_TEX_PTR(0) | - R300_RS_SEL_S(R300_RS_SEL_C0) | - R300_RS_SEL_T(R300_RS_SEL_C1) | - R300_RS_SEL_R(R300_RS_SEL_K0) | - R300_RS_SEL_Q(R300_RS_SEL_K1)); - END_BATCH(); -} - -static void emit_pvs_setup(struct r300_context *r300, - uint32_t *vp_code, - unsigned vp_len) -{ - BATCH_LOCALS(&r300->radeon); - - r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START); - - BEGIN_BATCH(4); - OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3); - OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) | - ((vp_len - 1) << R300_PVS_XYZW_VALID_INST_SHIFT) | - ((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT)); - OUT_BATCH(0); - OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT); - END_BATCH(); -} - -static void emit_vap_setup(struct r300_context *r300) -{ - int tex_offset; - BATCH_LOCALS(&r300->radeon); - - if (r300->options.hw_tcl_enabled) - tex_offset = 1; - else - tex_offset = 6; - - BEGIN_BATCH(12); - OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2); - OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT); - OUT_BATCH(4); - - OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); - OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) | - (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16)); - OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | - (0xf << R300_WRITE_ENA_SHIFT) ) << 0) | - (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | - (0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) ); - OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); - OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT); - OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS); - END_BATCH(); -} - -static GLboolean validate_buffers(struct r300_context *r300, - struct radeon_bo *src_bo, - struct radeon_bo *dst_bo) -{ - int ret; - - radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs); - - ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, - src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); - if (ret) - return GL_FALSE; - - ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, - dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); - if (ret) - return GL_FALSE; - - return GL_TRUE; -} - -/** - * Calculate texcoords for given image region. - * Output values are [minx, maxx, miny, maxy] - */ -static void calc_tex_coords(float img_width, float img_height, - float x, float y, - float reg_width, float reg_height, - unsigned flip_y, float *buf) -{ - buf[0] = x / img_width; - buf[1] = buf[0] + reg_width / img_width; - buf[2] = y / img_height; - buf[3] = buf[2] + reg_height / img_height; - if (flip_y) - { - buf[2] = 1.0 - buf[2]; - buf[3] = 1.0 - buf[3]; - } -} - -static void emit_draw_packet(struct r300_context *r300, - unsigned src_width, unsigned src_height, - unsigned src_x_offset, unsigned src_y_offset, - unsigned dst_x_offset, unsigned dst_y_offset, - unsigned reg_width, unsigned reg_height, - unsigned flip_y) -{ - float texcoords[4]; - - calc_tex_coords(src_width, src_height, - src_x_offset, src_y_offset, - reg_width, reg_height, - flip_y, texcoords); - - float verts[] = { dst_x_offset, dst_y_offset, - texcoords[0], texcoords[2], - dst_x_offset, dst_y_offset + reg_height, - texcoords[0], texcoords[3], - dst_x_offset + reg_width, dst_y_offset + reg_height, - texcoords[1], texcoords[3], - dst_x_offset + reg_width, dst_y_offset, - texcoords[1], texcoords[2] }; - - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH(19); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED | - (4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS); - OUT_BATCH_TABLE(verts, 16); - END_BATCH(); -} - -static void other_stuff(struct r300_context *r300) -{ - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH(13); - OUT_BATCH_REGVAL(R300_GA_POLY_MODE, - R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI); - OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW); - OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0); - OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0); - OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH_REGVAL(R300_ZB_CNTL, 0); - END_BATCH(); - if (r300->options.hw_tcl_enabled) { - BEGIN_BATCH(2); - OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); - END_BATCH(); - } -} - -static void emit_cb_setup(struct r300_context *r300, - struct radeon_bo *bo, - intptr_t offset, - gl_format mesa_format, - unsigned pitch, - unsigned width, - unsigned height) -{ - BATCH_LOCALS(&r300->radeon); - - unsigned x1, y1, x2, y2; - x1 = 0; - y1 = 0; - x2 = width - 1; - y2 = height - 1; - - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - x1 += R300_SCISSORS_OFFSET; - y1 += R300_SCISSORS_OFFSET; - x2 += R300_SCISSORS_OFFSET; - y2 += R300_SCISSORS_OFFSET; - } - - r300_emit_cb_setup(r300, bo, offset, mesa_format, - _mesa_get_format_bytes(mesa_format), - _mesa_format_row_stride(mesa_format, pitch)); - - BEGIN_BATCH_NO_AUTOSTATE(5); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); - OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0); - END_BATCH(); -} - -unsigned r300_check_blit(gl_format dst_format) -{ - switch (dst_format) { - case MESA_FORMAT_RGB565: - case MESA_FORMAT_ARGB1555: - case MESA_FORMAT_RGBA8888: - case MESA_FORMAT_RGBA8888_REV: - case MESA_FORMAT_ARGB8888: - case MESA_FORMAT_ARGB8888_REV: - case MESA_FORMAT_XRGB8888: - break; - default: - return 0; - } - - if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0) - return 0; - - return 1; -} - -/** - * Copy a region of [@a width x @a height] pixels from source buffer - * to destination buffer. - * @param[in] r300 r300 context - * @param[in] src_bo source radeon buffer object - * @param[in] src_offset offset of the source image in the @a src_bo - * @param[in] src_mesaformat source image format - * @param[in] src_pitch aligned source image width - * @param[in] src_width source image width - * @param[in] src_height source image height - * @param[in] src_x_offset x offset in the source image - * @param[in] src_y_offset y offset in the source image - * @param[in] dst_bo destination radeon buffer object - * @param[in] dst_offset offset of the destination image in the @a dst_bo - * @param[in] dst_mesaformat destination image format - * @param[in] dst_pitch aligned destination image width - * @param[in] dst_width destination image width - * @param[in] dst_height destination image height - * @param[in] dst_x_offset x offset in the destination image - * @param[in] dst_y_offset y offset in the destination image - * @param[in] width region width - * @param[in] height region height - * @param[in] flip_y set if y coords of the source image need to be flipped - */ -unsigned r300_blit(struct gl_context *ctx, - struct radeon_bo *src_bo, - intptr_t src_offset, - gl_format src_mesaformat, - unsigned src_pitch, - unsigned src_width, - unsigned src_height, - unsigned src_x_offset, - unsigned src_y_offset, - struct radeon_bo *dst_bo, - intptr_t dst_offset, - gl_format dst_mesaformat, - unsigned dst_pitch, - unsigned dst_width, - unsigned dst_height, - unsigned dst_x_offset, - unsigned dst_y_offset, - unsigned reg_width, - unsigned reg_height, - unsigned flip_y) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - if (!r300_check_blit(dst_mesaformat)) - return 0; - - /* Make sure that colorbuffer has even width - hw limitation */ - if (dst_pitch % 2 > 0) - ++dst_pitch; - - /* Need to clamp the region size to make sure - * we don't read outside of the source buffer - * or write outside of the destination buffer. - */ - if (reg_width + src_x_offset > src_width) - reg_width = src_width - src_x_offset; - if (reg_height + src_y_offset > src_height) - reg_height = src_height - src_y_offset; - if (reg_width + dst_x_offset > dst_width) - reg_width = dst_width - dst_x_offset; - if (reg_height + dst_y_offset > dst_height) - reg_height = dst_height - dst_y_offset; - - if (src_bo == dst_bo) { - return 0; - } - - if (src_offset % 32 || dst_offset % 32) { - return GL_FALSE; - } - - if (0) { - fprintf(stderr, "src: size [%d x %d], pitch %d, " - "offset [%d x %d], format %s, bo %p\n", - src_width, src_height, src_pitch, - src_x_offset, src_y_offset, - _mesa_get_format_name(src_mesaformat), - src_bo); - fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n", - dst_pitch, dst_x_offset, dst_y_offset, - _mesa_get_format_name(dst_mesaformat), dst_bo); - fprintf(stderr, "region: %d x %d\n", reg_width, reg_height); - } - - /* Flush is needed to make sure that source buffer has correct data */ - radeonFlush(r300->radeon.glCtx); - - if (!validate_buffers(r300, src_bo, dst_bo)) - return 0; - - rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__); - - other_stuff(r300); - - r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); - - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat); - r500_emit_rs_setup(r300); - } else { - r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat); - r300_emit_rs_setup(r300); - } - - if (r300->options.hw_tcl_enabled) - emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2); - - emit_vap_setup(r300); - - emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height); - - emit_draw_packet(r300, src_width, src_height, - src_x_offset, src_y_offset, - dst_x_offset, dst_y_offset, - reg_width, reg_height, - flip_y); - - r300EmitCacheFlush(r300); - - radeonFlush(r300->radeon.glCtx); - - return 1; -} diff --git a/src/mesa/drivers/dri/r300/r300_blit.h b/src/mesa/drivers/dri/r300/r300_blit.h deleted file mode 100644 index 286dbe18560..00000000000 --- a/src/mesa/drivers/dri/r300/r300_blit.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef R300_BLIT_H -#define R300_BLIT_H - -void r300_blit_init(struct r300_context *r300); - -unsigned r300_check_blit(gl_format mesa_format); - -unsigned r300_blit(struct gl_context *ctx, - struct radeon_bo *src_bo, - intptr_t src_offset, - gl_format src_mesaformat, - unsigned src_pitch, - unsigned src_width, - unsigned src_height, - unsigned src_x_offset, - unsigned src_y_offset, - struct radeon_bo *dst_bo, - intptr_t dst_offset, - gl_format dst_mesaformat, - unsigned dst_pitch, - unsigned dst_width, - unsigned dst_height, - unsigned dst_x_offset, - unsigned dst_y_offset, - unsigned reg_width, - unsigned reg_height, - unsigned flip_y); - -#endif // R300_BLIT_H diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c deleted file mode 100644 index 8a2f5ce0214..00000000000 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ /dev/null @@ -1,907 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Nicolai Haehnle <[email protected]> - */ - -#include "main/glheader.h" -#include "main/state.h" -#include "main/imports.h" -#include "main/macros.h" -#include "main/context.h" -#include "main/simple_list.h" - -#include "drm.h" -#include "radeon_drm.h" - -#include "r300_context.h" -#include "r300_reg.h" -#include "r300_cmdbuf.h" -#include "r300_emit.h" -#include "radeon_bocs_wrapper.h" -#include "radeon_mipmap_tree.h" -#include "radeon_queryobj.h" - -/** # of dwords reserved for additional instructions that may need to be written - * during flushing. - */ -#define SPACE_FOR_FLUSHING 4 - -static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) -{ - if (r300->radeon.radeonScreen->kernel_mm) { - return ((((*pkt) >> 16) & 0x3FFF) + 1); - } else { - drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; - return t->packet0.count; - } -} - -#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) -#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) - -static int check_vpu(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int cnt; - int extra = 1; - cnt = vpu_count(atom->cmd); - - if (r300->radeon.radeonScreen->kernel_mm) { - extra = 3; - } - - return cnt ? (cnt * 4) + extra : 0; -} - -static int check_vpp(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int cnt; - int extra = 1; - - if (r300->radeon.radeonScreen->kernel_mm) { - cnt = r300->selected_vp->code.constants.Count * 4; - extra = 3; - } else { - cnt = vpu_count(atom->cmd); - extra = 1; - } - - return cnt ? (cnt * 4) + extra : 0; -} - -void r300_emit_vpu(struct r300_context *r300, - uint32_t *data, - unsigned len, - uint32_t addr) -{ - BATCH_LOCALS(&r300->radeon); - - BEGIN_BATCH_NO_AUTOSTATE(3 + len); - OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR); - OUT_BATCH_TABLE(data, len); - END_BATCH(); -} - -static void emit_vpu_state(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - drm_r300_cmd_header_t cmd; - uint32_t addr; - - cmd.u = atom->cmd[0]; - addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; - - r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr); -} - -static void emit_vpp_state(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - drm_r300_cmd_header_t cmd; - uint32_t addr; - - cmd.u = atom->cmd[0]; - addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; - - r300_emit_vpu(r300, &atom->cmd[1], r300->selected_vp->code.constants.Count * 4, addr); -} - -void r500_emit_fp(struct r300_context *r300, - uint32_t *data, - unsigned len, - uint32_t addr, - unsigned type, - unsigned clamp) -{ - BATCH_LOCALS(&r300->radeon); - - addr |= (type << 16); - addr |= (clamp << 17); - - BEGIN_BATCH_NO_AUTOSTATE(len + 3); - OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); - OUT_BATCH(addr); - OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR); - OUT_BATCH_TABLE(data, len); - END_BATCH(); -} - -static void emit_r500fp_atom(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - drm_r300_cmd_header_t cmd; - uint32_t addr, count; - int type, clamp; - - cmd.u = atom->cmd[0]; - addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo; - type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); - clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); - - if (type) { - count = r500fp_count(atom->cmd) * 4; - } else { - count = r500fp_count(atom->cmd) * 6; - } - - r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp); -} - -static int check_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); - int dw = 0, i; - if (atom->cmd[0] == CP_PACKET2) { - return dw; - } - for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r300->hw.textures[i]; - if (!t && !r300->radeon.radeonScreen->kernel_mm) { - dw += 0; - } else if (t && t->image_override && !t->bo) { - if (!r300->radeon.radeonScreen->kernel_mm) - dw += 2; - } else - dw += 4; - } - return dw; -} - -static void emit_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); - int i; - - for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r300->hw.textures[i]; - if (t && !t->image_override) { - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); - } else if (!t) { - /* Texture unit hasn't a texture bound. - * We assign the current color buffer as a fakery to make - * KIL work on KMS (without it, the CS checker will complain). - */ - if (r300->radeon.radeonScreen->kernel_mm) { - struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon); - if (rrb && rrb->bo) { - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); - } - } - } else { /* override cases */ - if (t->bo) { - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); - } else if (!r300->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - OUT_BATCH(t->override_offset); - END_BATCH(); - } else { - /* Texture unit hasn't a texture bound nothings to do */ - } - } - } -} - -void r300_emit_scissor(struct gl_context *ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - unsigned x1, y1, x2, y2; - struct radeon_renderbuffer *rrb; - - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { - return; - } - rrb = radeon_get_colorbuffer(&r300->radeon); - if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; - } - if (r300->radeon.state.scissor.enabled) { - x1 = r300->radeon.state.scissor.rect.x1; - y1 = r300->radeon.state.scissor.rect.y1; - x2 = r300->radeon.state.scissor.rect.x2; - y2 = r300->radeon.state.scissor.rect.y2; - } else { - x1 = 0; - y1 = 0; - x2 = rrb->base.Width - 1; - y2 = rrb->base.Height - 1; - } - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - x1 += R300_SCISSORS_OFFSET; - y1 += R300_SCISSORS_OFFSET; - x2 += R300_SCISSORS_OFFSET; - y2 += R300_SCISSORS_OFFSET; - } - BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); - OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT)); - END_BATCH(); -} -static int check_cb_offset(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - uint32_t dw = 6 + 3 + 16; - if (r300->radeon.radeonScreen->kernel_mm) - dw += 2; - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { - dw -= 3 + 16; - } - return dw; -} - -static void emit_scissor(struct r300_context *r300, - unsigned width, - unsigned height) -{ - int i; - BATCH_LOCALS(&r300->radeon); - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); - OUT_BATCH(0); - OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) | - ((height - 1) << R300_SCISSORS_Y_SHIFT)); - END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(16); - for (i = 0; i < 4; i++) { - OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); - OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT)); - } - OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); - OUT_BATCH(0xAAAA); - OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1); - OUT_BATCH(0xffffff); - END_BATCH(); - } else { - BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); - OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | - (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) | - ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT)); - END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(16); - for (i = 0; i < 4; i++) { - OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); - OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) | - ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT)); - } - OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); - OUT_BATCH(0xAAAA); - OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1); - OUT_BATCH(0xffffff); - END_BATCH(); - } -} - -void r300_emit_cb_setup(struct r300_context *r300, - struct radeon_bo *bo, - uint32_t offset, - GLuint format, - unsigned cpp, - unsigned pitch) -{ - BATCH_LOCALS(&r300->radeon); - uint32_t cbpitch = pitch / cpp; - uint32_t dw = 6; - - assert(offset % 32 == 0); - - switch (format) { - case MESA_FORMAT_SL8: - case MESA_FORMAT_A8: - case MESA_FORMAT_L8: - case MESA_FORMAT_I8: - cbpitch |= R300_COLOR_FORMAT_I8; - break; - case MESA_FORMAT_RGB565: - case MESA_FORMAT_RGB565_REV: - cbpitch |= R300_COLOR_FORMAT_RGB565; - break; - case MESA_FORMAT_ARGB4444: - case MESA_FORMAT_ARGB4444_REV: - cbpitch |= R300_COLOR_FORMAT_ARGB4444; - break; - case MESA_FORMAT_RGBA5551: - case MESA_FORMAT_ARGB1555: - case MESA_FORMAT_ARGB1555_REV: - cbpitch |= R300_COLOR_FORMAT_ARGB1555; - break; - case MESA_FORMAT_RGBA8888: - case MESA_FORMAT_RGBA8888_REV: - case MESA_FORMAT_XRGB8888: - case MESA_FORMAT_ARGB8888: - case MESA_FORMAT_XRGB8888_REV: - case MESA_FORMAT_ARGB8888_REV: - case MESA_FORMAT_SRGBA8: - case MESA_FORMAT_SARGB8: - cbpitch |= R300_COLOR_FORMAT_ARGB8888; - break; - default: - _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()"); - break; - } - - if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= R300_COLOR_TILE_ENABLE; - - if (r300->radeon.radeonScreen->kernel_mm) - dw += 2; - - BEGIN_BATCH_NO_AUTOSTATE(dw); - OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); - if (!r300->radeon.radeonScreen->kernel_mm) - OUT_BATCH(cbpitch); - else - OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); - END_BATCH(); -} - -static void emit_cb_offset_atom(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct radeon_renderbuffer *rrb; - uint32_t offset = r300->radeon.state.color.draw_offset; - - rrb = radeon_get_colorbuffer(&r300->radeon); - if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; - } - - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height); - - r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch); - - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - emit_scissor(r300, rrb->base.Width, rrb->base.Height); - } -} - -static int check_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - uint32_t dw; - dw = 6; - if (r300->radeon.radeonScreen->kernel_mm) - dw += 2; - return dw; -} - -static void emit_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - struct radeon_renderbuffer *rrb; - uint32_t zbpitch; - uint32_t dw = atom->check(ctx, atom); - - rrb = radeon_get_depthbuffer(&r300->radeon); - if (!rrb) - return; - - zbpitch = (rrb->pitch / rrb->cpp); - if (!r300->radeon.radeonScreen->kernel_mm) { - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - zbpitch |= R300_DEPTHMACROTILE_ENABLE; - } - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - zbpitch |= R300_DEPTHMICROTILE_TILED; - } - } - - BEGIN_BATCH_NO_AUTOSTATE(dw); - OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1); - if (!r300->radeon.radeonScreen->kernel_mm) - OUT_BATCH(zbpitch); - else - OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); - END_BATCH(); -} - -static void emit_zstencil_format(struct gl_context *ctx, struct radeon_state_atom * atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - struct radeon_renderbuffer *rrb; - uint32_t format = 0; - - rrb = radeon_get_depthbuffer(&r300->radeon); - if (!rrb) - format = 0; - else { - if (rrb->cpp == 2) - format = R300_DEPTHFORMAT_16BIT_INT_Z; - else if (rrb->cpp == 4) - format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; - } - - BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size); - OUT_BATCH(atom->cmd[0]); - atom->cmd[1] &= ~0xf; - atom->cmd[1] |= format; - OUT_BATCH(atom->cmd[1]); - OUT_BATCH(atom->cmd[2]); - OUT_BATCH(atom->cmd[3]); - OUT_BATCH(atom->cmd[4]); - END_BATCH(); -} - -static int check_never(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - return 0; -} - -static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - return atom->cmd_size; -} - -static int check_variable(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int cnt; - if (atom->cmd[0] == CP_PACKET2) { - return 0; - } - cnt = packet0_count(r300, atom->cmd); - return cnt ? cnt + 1 : 0; -} - -static int check_r500fp(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - int cnt; - r300ContextPtr r300 = R300_CONTEXT(ctx); - int extra = 1; - cnt = r500fp_count(atom->cmd); - if (r300->radeon.radeonScreen->kernel_mm) - extra = 3; - - return cnt ? (cnt * 6) + extra : 0; -} - -static int check_r500fp_const(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - int cnt; - r300ContextPtr r300 = R300_CONTEXT(ctx); - int extra = 1; - cnt = r500fp_count(atom->cmd); - if (r300->radeon.radeonScreen->kernel_mm) - extra = 3; - - cnt = r500fp_count(atom->cmd); - return cnt ? (cnt * 4) + extra : 0; -} - -#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ - do { \ - r300->hw.ATOM.cmd_size = (SZ); \ - r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \ - r300->hw.ATOM.name = #ATOM; \ - r300->hw.ATOM.idx = (IDX); \ - r300->hw.ATOM.check = check_##CHK; \ - r300->hw.ATOM.dirty = GL_FALSE; \ - r300->radeon.hw.max_state_size += (SZ); \ - insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \ - } while (0) -/** - * Allocate memory for the command buffer and initialize the state atom - * list. Note that the initial hardware state is set by r300InitState(). - */ -void r300InitCmdBuf(r300ContextPtr r300) -{ - int mtu; - int has_tcl; - int is_r500 = 0; - - has_tcl = r300->options.hw_tcl_enabled; - - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; - - r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ - - mtu = r300->radeon.glCtx->Const.MaxTextureUnits; - if (RADEON_DEBUG & RADEON_TEXTURE) { - fprintf(stderr, "Using %d maximum texture units..\n", mtu); - } - - /* Setup the atom linked list */ - make_empty_list(&r300->radeon.hw.atomlist); - r300->radeon.hw.atomlist.name = "atom-list"; - - /* Initialize state atoms */ - ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); - r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6); - ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0); - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1); - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0; - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1); - if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) { - ALLOC_STATE(vap_index_offset, always, 2, 0); - r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); - r300->hw.vap_index_offset.cmd[1] = 0; - } - ALLOC_STATE(vte, always, 3, 0); - r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2); - ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); - r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2); - ALLOC_STATE(vap_cntl_status, always, 2, 0); - r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1); - ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0); - r300->hw.vir[0].cmd[R300_VIR_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1); - ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1); - r300->hw.vir[1].cmd[R300_VIR_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1); - ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0); - r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2); - ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); - r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); - - if (has_tcl) { - ALLOC_STATE(vap_clip_cntl, always, 2, 0); - r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1); - ALLOC_STATE(vap_clip, always, 5, 0); - r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4); - ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); - r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); - } - - ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0); - r300->hw.vof.cmd[R300_VOF_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2); - - if (has_tcl) { - ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0); - r300->hw.pvs.cmd[R300_PVS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3); - } - - ALLOC_STATE(gb_enable, always, 2, 0); - r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1); - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { - ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0); - } else { - ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0); - } - r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3); - ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0); - r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2); - ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0); - r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1); - ALLOC_STATE(ga_point_s0, always, 5, 0); - r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4); - ALLOC_STATE(ga_triangle_stipple, always, 2, 0); - r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1); - ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0); - r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1); - ALLOC_STATE(ga_point_minmax, always, 4, 0); - r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3); - ALLOC_STATE(lcntl, always, 2, 0); - r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1); - ALLOC_STATE(ga_line_stipple, always, 4, 0); - r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3); - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { - ALLOC_STATE(shade, always, 2, 0); - } else { - ALLOC_STATE(shade, never, 2, 0); - } - r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1); - ALLOC_STATE(shade2, always, 4, 0); - r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3); - ALLOC_STATE(polygon_mode, always, 4, 0); - r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3); - ALLOC_STATE(fogp, always, 3, 0); - r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2); - ALLOC_STATE(zbias_cntl, always, 2, 0); - r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1); - ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0); - r300->hw.zbs.cmd[R300_ZBS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4); - ALLOC_STATE(occlusion_cntl, always, 2, 0); - r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1); - ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0); - r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1); - ALLOC_STATE(su_depth_scale, always, 3, 0); - r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2); - ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0); - r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2); - if (is_r500) { - ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16); - ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1); - } else { - ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8); - ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1); - } - ALLOC_STATE(sc_hyperz, always, 3, 0); - r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2); - ALLOC_STATE(sc_screendoor, always, 2, 0); - r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1); - ALLOC_STATE(us_out_fmt, always, 6, 0); - r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5); - - if (is_r500) { - ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2); - r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; - r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3); - r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1); - r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ - - ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); - r300->hw.r500fp.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.r500fp.emit = emit_r500fp_atom; - - ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); - r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.r500fp_const.emit = emit_r500fp_atom; - } else { - ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3); - r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4); - - ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0); - r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0); - - ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0); - r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1); - ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1); - r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1); - ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2); - r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1); - ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3); - r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1); - ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0); - r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0); - } - ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0); - r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1); - ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0); - r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3); - ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0); - r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2); - ALLOC_STATE(fg_depth_src, always, 2, 0); - r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1); - ALLOC_STATE(rb3d_cctl, always, 2, 0); - r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1); - ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0); - r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2); - ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0); - r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); - if (is_r500) { - ALLOC_STATE(blend_color, always, 3, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); - } else { - ALLOC_STATE(blend_color, always, 2, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1); - } - ALLOC_STATE(rop, always, 2, 0); - r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1); - ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0); - r300->hw.cb.emit = &emit_cb_offset_atom; - ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); - r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); - ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); - r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) { - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - } else { - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0); - } - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); - ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); - r300->hw.zs.cmd[R300_ZS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); - if (is_r500) { - if (r300->radeon.radeonScreen->kernel_mm) - ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0); - else - ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0); - r300->hw.zsb.cmd[R300_ZSB_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1); - } - - ALLOC_STATE(zstencil_format, always, 5, 0); - r300->hw.zstencil_format.cmd[0] = - cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4); - r300->hw.zstencil_format.emit = emit_zstencil_format; - - ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0); - r300->hw.zb.emit = emit_zb_offset; - ALLOC_STATE(zb_depthclearvalue, always, 2, 0); - r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1); - ALLOC_STATE(zb_zmask, always, 3, 0); - r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2); - ALLOC_STATE(zb_hiz_offset, always, 2, 0); - r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1); - ALLOC_STATE(zb_hiz_pitch, always, 2, 0); - r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1); - - /* VPU only on TCL */ - if (has_tcl) { - int i; - ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0); - r300->hw.vpi.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vpi.emit = emit_vpu_state; - - if (is_r500) { - ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vpp.emit = emit_vpp_state; - - ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vps.emit = emit_vpu_state; - - for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[0] = - cmdvpu(r300->radeon.radeonScreen, - R500_PVS_UCP_START + i, 1); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vpucp[i].emit = emit_vpu_state; - } - } else { - ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vpp.emit = emit_vpp_state; - - ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vps.emit = emit_vpu_state; - - for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[0] = - cmdvpu(r300->radeon.radeonScreen, - R300_PVS_UCP_START + i, 1); - if (r300->radeon.radeonScreen->kernel_mm) - r300->hw.vpucp[i].emit = emit_vpu_state; - } - } - } - - /* Textures */ - ALLOC_STATE(tex.filter, variable, mtu + 1, 0); - r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0); - - ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0); - r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0); - - ALLOC_STATE(tex.size, variable, mtu + 1, 0); - r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0); - - ALLOC_STATE(tex.format, variable, mtu + 1, 0); - r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0); - - ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); - r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0); - - ALLOC_STATE(tex.offset, tex_offsets, 1, 0); - r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0); - r300->hw.tex.offset.emit = &emit_tex_offsets; - - ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); - r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0); - - ALLOC_STATE(tex.border_color, variable, mtu + 1, 0); - r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); - - radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE); - if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) { - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1); - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL; - } else { - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1); - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL; - } - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1); - r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0; - - r300->radeon.hw.is_dirty = GL_TRUE; - r300->radeon.hw.all_dirty = GL_TRUE; - - rcommonInitCmdBuf(&r300->radeon); -} diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h deleted file mode 100644 index 7e6b8c5de62..00000000000 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Nicolai Haehnle <[email protected]> - */ - -#ifndef __R300_CMDBUF_H__ -#define __R300_CMDBUF_H__ - -#include "r300_context.h" - -#define CACHE_FLUSH_BUFSZ (4*2) -#define PRE_EMIT_STATE_BUFSZ (2+2) -#define AOS_BUFSZ(nr) (3+(nr >>1)*3 + (nr&1)*2 + (nr*2)) -#define FIREAOS_BUFSZ (3) -#define SCISSORS_BUFSZ (3) - -void r300InitCmdBuf(r300ContextPtr r300); -void r300_emit_scissor(struct gl_context *ctx); - -void r300_emit_vpu(struct r300_context *ctx, - uint32_t *data, - unsigned len, - uint32_t addr); - -void r500_emit_fp(struct r300_context *r300, - uint32_t *data, - unsigned len, - uint32_t addr, - unsigned type, - unsigned clamp); - -void r300_emit_cb_setup(struct r300_context *r300, - struct radeon_bo *bo, - uint32_t offset, - GLuint format, - unsigned cpp, - unsigned pitch); - -#endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c deleted file mode 100644 index 9d9bfc3ef89..00000000000 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ /dev/null @@ -1,526 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Keith Whitwell <[email protected]> - * - * \author Nicolai Haehnle <[email protected]> - */ - -#include <stdbool.h> -#include "main/glheader.h" -#include "main/api_arrayelt.h" -#include "main/context.h" -#include "main/simple_list.h" -#include "main/imports.h" -#include "main/extensions.h" -#include "main/bufferobj.h" -#include "main/texobj.h" -#include "main/mfeatures.h" - -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "vbo/vbo.h" - -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -#include "drivers/common/driverfuncs.h" -#include "drivers/common/meta.h" - -#include "r300_context.h" -#include "radeon_span.h" -#include "r300_blit.h" -#include "r300_cmdbuf.h" -#include "r300_state.h" -#include "r300_tex.h" -#include "r300_emit.h" -#include "r300_render.h" -#include "r300_swtcl.h" -#include "radeon_bocs_wrapper.h" -#include "radeon_buffer_objects.h" -#include "radeon_queryobj.h" - -#include "utils.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ - - -static const struct tnl_pipeline_stage *r300_pipeline[] = { - /* Catch any t&l fallbacks - */ - &_tnl_vertex_transform_stage, - &_tnl_normal_transform_stage, - &_tnl_lighting_stage, - &_tnl_fog_coordinate_stage, - &_tnl_texgen_stage, - &_tnl_texture_transform_stage, - &_tnl_point_attenuation_stage, - &_tnl_vertex_program_stage, - &_tnl_render_stage, - 0, -}; - -static void r300_get_lock(radeonContextPtr rmesa) -{ - drm_radeon_sarea_t *sarea = rmesa->sarea; - - if (sarea->ctx_owner != rmesa->dri.hwContext) { - sarea->ctx_owner = rmesa->dri.hwContext; - if (!rmesa->radeonScreen->kernel_mm) - radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); - } -} - -static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) -{ - /* please flush pipe do all pending work */ - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_SCREENDOOR, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_SCREENDOOR, 1)); - radeon_cs_write_dword(cs, 0x00FFFFFF); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_HYPERZ, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_US_CONFIG, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_ZB_CNTL, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_RB3D_DSTCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_ZB_ZCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); - radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, - R300_WAIT_3D | R300_WAIT_3D_CLEAN)); -} - -static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - - cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); - END_BATCH(); - end_3d(radeon); -} - -static void r300_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - if (mode) - r300->radeon.Fallback |= bit; - else - r300->radeon.Fallback &= ~bit; - - r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode); -} - -static void r300_emit_query_finish(radeonContextPtr radeon) -{ - r300ContextPtr r300 = (r300ContextPtr)radeon; - struct radeon_query_object *query = radeon->query.current; - BATCH_LOCALS(radeon); - - BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2); - switch (r300->radeon.radeonScreen->num_gb_pipes) { - case 4: - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0); - case 3: - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0); - case 2: - if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) { - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3); - } else { - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1); - } - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0); - case 1: - default: - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); - break; - } - OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL); - END_BATCH(); - query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t); - assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); - query->emitted_begin = GL_FALSE; -} - -static void rv530_emit_query_finish_single_z(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - struct radeon_query_object *query = radeon->query.current; - - BEGIN_BATCH_NO_AUTOSTATE(8); - OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); - OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); - END_BATCH(); - - query->curr_offset += sizeof(uint32_t); - assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); - query->emitted_begin = GL_FALSE; -} - -static void rv530_emit_query_finish_double_z(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - struct radeon_query_object *query = radeon->query.current; - - BEGIN_BATCH_NO_AUTOSTATE(14); - OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); - OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1); - OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1); - OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0); - OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); - END_BATCH(); - - query->curr_offset += 2 * sizeof(uint32_t); - assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); - query->emitted_begin = GL_FALSE; -} - -static void r300_init_vtbl(radeonContextPtr radeon) -{ - radeon->vtbl.get_lock = r300_get_lock; - radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; - radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; - radeon->vtbl.swtcl_flush = r300_swtcl_flush; - radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; - radeon->vtbl.fallback = r300_fallback; - if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) { - if (radeon->radeonScreen->num_z_pipes == 2) - radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z; - else - radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z; - } else - radeon->vtbl.emit_query_finish = r300_emit_query_finish; - - radeon->vtbl.check_blit = r300_check_blit; - radeon->vtbl.blit = r300_blit; - - if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - radeon->vtbl.is_format_renderable = r500IsFormatRenderable; - } else { - radeon->vtbl.is_format_renderable = r300IsFormatRenderable; - } -} - -static void r300InitConstValues(struct gl_context *ctx, radeonScreenPtr screen) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - ctx->Const.MaxTextureImageUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_image_units"); - ctx->Const.MaxTextureCoordUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); - ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits, - ctx->Const.MaxTextureCoordUnits); - ctx->Const.MaxCombinedTextureImageUnits = - ctx->Const.MaxVertexTextureImageUnits + - ctx->Const.MaxTextureImageUnits; - - - ctx->Const.MaxTextureMaxAnisotropy = 16.0; - ctx->Const.MaxTextureLodBias = 16.0; - - if (screen->chip_family >= CHIP_FAMILY_RV515) { - ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxCubeTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; - ctx->Const.MaxRenderbufferSize = 4096; - } - else { - ctx->Const.MaxTextureLevels = 12; - ctx->Const.MaxCubeTextureLevels = 12; - ctx->Const.MaxTextureRectSize = 2048; - ctx->Const.MaxRenderbufferSize = 2048; - } - - ctx->Const.MinPointSize = 1.0; - ctx->Const.MinPointSizeAA = 1.0; - ctx->Const.MaxPointSize = R300_POINTSIZE_MAX; - ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX; - - ctx->Const.MinLineWidth = 1.0; - ctx->Const.MinLineWidthAA = 1.0; - ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; - ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; - - ctx->Const.MaxDrawBuffers = 1; - ctx->Const.MaxColorAttachments = 1; - - if (r300->options.hw_tcl_enabled) { - ctx->Const.VertexProgram.MaxNativeInstructions = 255; - ctx->Const.VertexProgram.MaxNativeAluInstructions = 255; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; - ctx->Const.VertexProgram.MaxNativeTemps = 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - } - - if (screen->chip_family >= CHIP_FAMILY_RV515) { - ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - - /* The hardware limits are higher than this, - * but the non-KMS DRM interface artificially limits us - * to this many instructions. - * - * We could of course work around it in the KMS path, - * but it would be a mess, so it seems wiser - * to leave it as is. Going forward, the Gallium driver - * will not be subject to these limitations. - */ - ctx->Const.FragmentProgram.MaxNativeParameters = 255; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255; - ctx->Const.FragmentProgram.MaxNativeInstructions = 255; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255; - ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; - } else { - ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT; - ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; - } - -} - -static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen) -{ - struct r300_options options = { 0 }; - - driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, - screen->driScreen->myNum, "r300"); - - r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); - - options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side"); - options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable"); - options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc"); - - if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW) - options.hw_tcl_enabled = 0; - else - options.hw_tcl_enabled = 1; - - options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); - - r300->options = options; -} - -static void r300InitGLExtensions(struct gl_context *ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - ctx->Extensions.ARB_depth_texture = true; - ctx->Extensions.ARB_fragment_program = true; - ctx->Extensions.ARB_shadow = true; - ctx->Extensions.ARB_shadow_ambient = true; - ctx->Extensions.ARB_texture_border_clamp = true; - ctx->Extensions.ARB_texture_cube_map = true; - ctx->Extensions.ARB_texture_env_combine = true; - ctx->Extensions.ARB_texture_env_crossbar = true; - ctx->Extensions.ARB_texture_env_dot3 = true; - ctx->Extensions.ARB_vertex_program = true; - ctx->Extensions.EXT_blend_color = true; - ctx->Extensions.EXT_blend_equation_separate = true; - ctx->Extensions.EXT_blend_func_separate = true; - ctx->Extensions.EXT_blend_minmax = true; - ctx->Extensions.EXT_fog_coord = true; - ctx->Extensions.EXT_gpu_program_parameters = true; - ctx->Extensions.EXT_point_parameters = true; - ctx->Extensions.EXT_provoking_vertex = true; - ctx->Extensions.EXT_secondary_color = true; - ctx->Extensions.EXT_shadow_funcs = true; - ctx->Extensions.EXT_texture_env_dot3 = true; - ctx->Extensions.EXT_texture_filter_anisotropic = true; - ctx->Extensions.EXT_texture_mirror_clamp = true; - ctx->Extensions.EXT_texture_sRGB = true; - ctx->Extensions.EXT_vertex_array_bgra = true; - ctx->Extensions.ATI_separate_stencil = true; - ctx->Extensions.ATI_texture_env_combine3 = true; - ctx->Extensions.ATI_texture_mirror_once = true; - ctx->Extensions.MESA_pack_invert = true; - ctx->Extensions.MESA_ycbcr_texture = true; - ctx->Extensions.NV_blend_square = true; - ctx->Extensions.NV_texture_rectangle = true; - ctx->Extensions.NV_vertex_program = true; -#if FEATURE_OES_EGL_image - ctx->Extensions.OES_EGL_image = true; -#endif - - if (r300->radeon.radeonScreen->kernel_mm) { - ctx->Extensions.EXT_framebuffer_blit = true; - ctx->Extensions.EXT_framebuffer_object = true; - } - - ctx->Extensions.EXT_stencil_two_side = - !r300->options.stencil_two_side_disabled; - - if (r300->options.s3tc_force_disabled) { - ctx->Extensions.EXT_texture_compression_s3tc = false; - } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) { - ctx->Extensions.EXT_texture_compression_s3tc = true; - ctx->Extensions.S3_s3tc = true; - } - - ctx->Extensions.ARB_occlusion_query = - r300->radeon.radeonScreen->drmSupportsOcclusionQueries; - - ctx->Extensions.ARB_half_float_vertex = - (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420); - - ctx->Extensions.EXT_packed_depth_stencil = - (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515); -} - -static void r300InitIoctlFuncs(struct dd_function_table *functions) -{ - functions->Clear = _mesa_meta_Clear; - functions->Finish = radeonFinish; - functions->Flush = radeonFlush; -} - -/* Create the device specific rendering context. - */ -GLboolean r300CreateContext(gl_api api, - const struct gl_config * glVisual, - __DRIcontext * driContextPriv, - void *sharedContextPrivate) -{ - __DRIscreen *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - struct dd_function_table functions; - r300ContextPtr r300; - struct gl_context *ctx; - - assert(glVisual); - assert(driContextPriv); - assert(screen); - - r300 = (r300ContextPtr) CALLOC(sizeof(*r300)); - if (!r300) - return GL_FALSE; - - r300ParseOptions(r300, screen); - - r300->radeon.radeonScreen = screen; - r300_init_vtbl(&r300->radeon); - - _mesa_init_driver_functions(&functions); - r300InitIoctlFuncs(&functions); - r300InitStateFuncs(&r300->radeon, &functions); - r300InitTextureFuncs(&r300->radeon, &functions); - r300InitShaderFuncs(&functions); - radeonInitQueryObjFunctions(&functions); - radeonInitBufferObjectFuncs(&functions); - - if (!radeonInitContext(&r300->radeon, &functions, - glVisual, driContextPriv, - sharedContextPrivate)) { - FREE(r300); - return GL_FALSE; - } - - ctx = r300->radeon.glCtx; - - r300->fallback = 0; - if (r300->options.hw_tcl_enabled) - ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; - - ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; - - r300InitConstValues(ctx, screen); - - _mesa_set_mvp_with_dp4( ctx, GL_TRUE ); - - /* Initialize the software rasterizer and helper modules. - */ - _swrast_CreateContext(ctx); - _vbo_CreateContext(ctx); - _tnl_CreateContext(ctx); - _swsetup_CreateContext(ctx); - _swsetup_Wakeup(ctx); - - /* Install the customized pipeline: - */ - _tnl_destroy_pipeline(ctx); - _tnl_install_pipeline(ctx, r300_pipeline); - TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; - - /* Configure swrast and TNL to match hardware characteristics: - */ - _swrast_allow_pixel_fog(ctx, GL_FALSE); - _swrast_allow_vertex_fog(ctx, GL_TRUE); - _tnl_allow_pixel_fog(ctx, GL_FALSE); - _tnl_allow_vertex_fog(ctx, GL_TRUE); - - if (r300->options.hw_tcl_enabled) { - r300InitDraw(ctx); - } else { - r300InitSwtcl(ctx); - } - - r300_blit_init(r300); - radeon_fbo_init(&r300->radeon); - radeonInitSpanFuncs( ctx ); - r300InitCmdBuf(r300); - r300InitState(r300); - r300InitShaderFunctions(r300); - - r300InitGLExtensions(ctx); - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h deleted file mode 100644 index 349a3d412f1..00000000000 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ /dev/null @@ -1,560 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Keith Whitwell <[email protected]> - * \author Nicolai Haehnle <[email protected]> - */ - -#ifndef __R300_CONTEXT_H__ -#define __R300_CONTEXT_H__ - -#include "drm.h" -#include "radeon_drm.h" -#include "dri_util.h" -#include "radeon_common.h" - -#include "main/mtypes.h" -#include "program/prog_instruction.h" -#include "compiler/radeon_code.h" - -struct r300_context; -typedef struct r300_context r300ContextRec; -typedef struct r300_context *r300ContextPtr; - - -#include "r300_vertprog.h" - - -/* The blit width for texture uploads - */ -#define R300_BLIT_WIDTH_BYTES 1024 -#define R300_MAX_TEXTURE_UNITS 8 - - - -#define R300_VPT_CMD_0 0 -#define R300_VPT_XSCALE 1 -#define R300_VPT_XOFFSET 2 -#define R300_VPT_YSCALE 3 -#define R300_VPT_YOFFSET 4 -#define R300_VPT_ZSCALE 5 -#define R300_VPT_ZOFFSET 6 -#define R300_VPT_CMDSIZE 7 - -#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */ -#define R300_VIR_CNTL_0 1 -#define R300_VIR_CNTL_1 2 -#define R300_VIR_CNTL_2 3 -#define R300_VIR_CNTL_3 4 -#define R300_VIR_CNTL_4 5 -#define R300_VIR_CNTL_5 6 -#define R300_VIR_CNTL_6 7 -#define R300_VIR_CNTL_7 8 -#define R300_VIR_CMDSIZE 9 - -#define R300_VIC_CMD_0 0 -#define R300_VIC_CNTL_0 1 -#define R300_VIC_CNTL_1 2 -#define R300_VIC_CMDSIZE 3 - -#define R300_VOF_CMD_0 0 -#define R300_VOF_CNTL_0 1 -#define R300_VOF_CNTL_1 2 -#define R300_VOF_CMDSIZE 3 - -#define R300_PVS_CMD_0 0 -#define R300_PVS_CNTL_1 1 -#define R300_PVS_CNTL_2 2 -#define R300_PVS_CNTL_3 3 -#define R300_PVS_CMDSIZE 4 - -#define R300_GB_MISC_CMD_0 0 -#define R300_GB_MISC_MSPOS_0 1 -#define R300_GB_MISC_MSPOS_1 2 -#define R300_GB_MISC_TILE_CONFIG 3 -#define R300_GB_MISC_CMDSIZE 4 -#define R300_GB_MISC2_CMD_0 0 -#define R300_GB_MISC2_SELECT 1 -#define R300_GB_MISC2_AA_CONFIG 2 -#define R300_GB_MISC2_CMDSIZE 3 - -#define R300_TXE_CMD_0 0 -#define R300_TXE_ENABLE 1 -#define R300_TXE_CMDSIZE 2 - -#define R300_PS_CMD_0 0 -#define R300_PS_POINTSIZE 1 -#define R300_PS_CMDSIZE 2 - -#define R300_ZBS_CMD_0 0 -#define R300_ZBS_T_FACTOR 1 -#define R300_ZBS_T_CONSTANT 2 -#define R300_ZBS_W_FACTOR 3 -#define R300_ZBS_W_CONSTANT 4 -#define R300_ZBS_CMDSIZE 5 - -#define R300_CUL_CMD_0 0 -#define R300_CUL_CULL 1 -#define R300_CUL_CMDSIZE 2 - -#define R300_RC_CMD_0 0 -#define R300_RC_CNTL_0 1 -#define R300_RC_CNTL_1 2 -#define R300_RC_CMDSIZE 3 - -#define R300_RI_CMD_0 0 -#define R300_RI_INTERP_0 1 -#define R300_RI_INTERP_1 2 -#define R300_RI_INTERP_2 3 -#define R300_RI_INTERP_3 4 -#define R300_RI_INTERP_4 5 -#define R300_RI_INTERP_5 6 -#define R300_RI_INTERP_6 7 -#define R300_RI_INTERP_7 8 -#define R300_RI_CMDSIZE 9 - -#define R500_RI_CMDSIZE 17 - -#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */ -#define R300_RR_INST_0 1 -#define R300_RR_INST_1 2 -#define R300_RR_INST_2 3 -#define R300_RR_INST_3 4 -#define R300_RR_INST_4 5 -#define R300_RR_INST_5 6 -#define R300_RR_INST_6 7 -#define R300_RR_INST_7 8 -#define R300_RR_CMDSIZE 9 - -#define R300_FP_CMD_0 0 -#define R300_FP_CNTL0 1 -#define R300_FP_CNTL1 2 -#define R300_FP_CNTL2 3 -#define R300_FP_CMD_1 4 -#define R300_FP_NODE0 5 -#define R300_FP_NODE1 6 -#define R300_FP_NODE2 7 -#define R300_FP_NODE3 8 -#define R300_FP_CMDSIZE 9 - -#define R500_FP_CMD_0 0 -#define R500_FP_CNTL 1 -#define R500_FP_PIXSIZE 2 -#define R500_FP_CMD_1 3 -#define R500_FP_CODE_ADDR 4 -#define R500_FP_CODE_RANGE 5 -#define R500_FP_CODE_OFFSET 6 -#define R500_FP_CMD_2 7 -#define R500_FP_FC_CNTL 8 -#define R500_FP_CMDSIZE 9 - -#define R300_FPT_CMD_0 0 -#define R300_FPT_INSTR_0 1 -#define R300_FPT_CMDSIZE 65 - -#define R300_FPI_CMD_0 0 -#define R300_FPI_INSTR_0 1 -#define R300_FPI_CMDSIZE 65 -/* R500 has space for 512 instructions - 6 dwords per instruction */ -#define R500_FPI_CMDSIZE (512*6+1) - -#define R300_FPP_CMD_0 0 -#define R300_FPP_PARAM_0 1 -#define R300_FPP_CMDSIZE (32*4+1) -/* R500 has spcae for 256 constants - 4 dwords per constant */ -#define R500_FPP_CMDSIZE (256*4+1) - -#define R300_FOGS_CMD_0 0 -#define R300_FOGS_STATE 1 -#define R300_FOGS_CMDSIZE 2 - -#define R300_FOGC_CMD_0 0 -#define R300_FOGC_R 1 -#define R300_FOGC_G 2 -#define R300_FOGC_B 3 -#define R300_FOGC_CMDSIZE 4 - -#define R300_FOGP_CMD_0 0 -#define R300_FOGP_SCALE 1 -#define R300_FOGP_START 2 -#define R300_FOGP_CMDSIZE 3 - -#define R300_AT_CMD_0 0 -#define R300_AT_ALPHA_TEST 1 -#define R300_AT_UNKNOWN 2 -#define R300_AT_CMDSIZE 3 - -#define R300_BLD_CMD_0 0 -#define R300_BLD_CBLEND 1 -#define R300_BLD_ABLEND 2 -#define R300_BLD_CMDSIZE 3 - -#define R300_CMK_CMD_0 0 -#define R300_CMK_COLORMASK 1 -#define R300_CMK_CMDSIZE 2 - -#define R300_CB_CMD_0 0 -#define R300_CB_OFFSET 1 -#define R300_CB_CMD_1 2 -#define R300_CB_PITCH 3 -#define R300_CB_CMDSIZE 4 - -#define R300_ZS_CMD_0 0 -#define R300_ZS_CNTL_0 1 -#define R300_ZS_CNTL_1 2 -#define R300_ZS_CNTL_2 3 -#define R300_ZS_CMDSIZE 4 - -#define R300_ZSB_CMD_0 0 -#define R300_ZSB_CNTL_0 1 -#define R300_ZSB_CMDSIZE 2 - -#define R300_ZB_CMD_0 0 -#define R300_ZB_OFFSET 1 -#define R300_ZB_PITCH 2 -#define R300_ZB_CMDSIZE 3 - -#define R300_VAP_CNTL_FLUSH 0 -#define R300_VAP_CNTL_FLUSH_1 1 -#define R300_VAP_CNTL_CMD 2 -#define R300_VAP_CNTL_INSTR 3 -#define R300_VAP_CNTL_SIZE 4 - -#define R300_VPI_CMD_0 0 -#define R300_VPI_INSTR_0 1 -#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */ - -#define R300_VPP_CMD_0 0 -#define R300_VPP_PARAM_0 1 -#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */ - -#define R300_VPUCP_CMD_0 0 -#define R300_VPUCP_X 1 -#define R300_VPUCP_Y 2 -#define R300_VPUCP_Z 3 -#define R300_VPUCP_W 4 -#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */ - -#define R300_VPS_CMD_0 0 -#define R300_VPS_ZERO_0 1 -#define R300_VPS_ZERO_1 2 -#define R300_VPS_POINTSIZE 3 -#define R300_VPS_ZERO_3 4 -#define R300_VPS_CMDSIZE 5 - - /* the layout is common for all fields inside tex */ -#define R300_TEX_CMD_0 0 -#define R300_TEX_VALUE_0 1 -/* We don't really use this, instead specify mtu+1 dynamically -#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1) -*/ - -#define R300_QUERYOBJ_CMD_0 0 -#define R300_QUERYOBJ_DATA_0 1 -#define R300_QUERYOBJ_CMD_1 2 -#define R300_QUERYOBJ_DATA_1 3 -#define R300_QUERYOBJ_CMDSIZE 4 - -/** - * Cache for hardware register state. - */ -struct r300_hw_state { - struct radeon_state_atom vpt; /* viewport (1D98) */ - struct radeon_state_atom vap_cntl; - struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ - struct radeon_state_atom vof; /* VAP output format register 0x2090 */ - struct radeon_state_atom vte; /* (20B0) */ - struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ - struct radeon_state_atom vap_cntl_status; - struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */ - struct radeon_state_atom vic; /* vap input control (2180) */ - struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ - struct radeon_state_atom vap_clip_cntl; - struct radeon_state_atom vap_clip; - struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ - struct radeon_state_atom pvs; /* pvs_cntl (22D0) */ - struct radeon_state_atom gb_enable; /* (4008) */ - struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ - struct radeon_state_atom gb_misc2; /* Multisampling position shifts ? (4010) */ - struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ - struct radeon_state_atom ga_triangle_stipple; /* (4214) */ - struct radeon_state_atom ps; /* pointsize (421C) */ - struct radeon_state_atom ga_point_minmax; /* (4230) */ - struct radeon_state_atom lcntl; /* line control */ - struct radeon_state_atom ga_line_stipple; /* (4260) */ - struct radeon_state_atom shade; - struct radeon_state_atom shade2; - struct radeon_state_atom polygon_mode; - struct radeon_state_atom fogp; /* fog parameters (4294) */ - struct radeon_state_atom ga_soft_reset; /* (429C) */ - struct radeon_state_atom zbias_cntl; - struct radeon_state_atom zbs; /* zbias (42A4) */ - struct radeon_state_atom occlusion_cntl; - struct radeon_state_atom cul; /* cull cntl (42B8) */ - struct radeon_state_atom su_depth_scale; /* (42C0) */ - struct radeon_state_atom rc; /* rs control (4300) */ - struct radeon_state_atom ri; /* rs interpolators (4310) */ - struct radeon_state_atom rr; /* rs route (4330) */ - struct radeon_state_atom sc_hyperz; /* (43A4) */ - struct radeon_state_atom sc_screendoor; /* (43E8) */ - struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */ - struct radeon_state_atom fpt; /* texi - (4620) */ - struct radeon_state_atom us_out_fmt; /* (46A4) */ - struct radeon_state_atom r500fp; /* r500 fp instructions */ - struct radeon_state_atom r500fp_const; /* r500 fp constants */ - struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ - struct radeon_state_atom fogs; /* fog state (4BC0) */ - struct radeon_state_atom fogc; /* fog color (4BC8) */ - struct radeon_state_atom at; /* alpha test (4BD4) */ - struct radeon_state_atom fg_depth_src; /* (4BD8) */ - struct radeon_state_atom fpp; /* 0x4C00 and following */ - struct radeon_state_atom rb3d_cctl; /* (4E00) */ - struct radeon_state_atom bld; /* blending (4E04) */ - struct radeon_state_atom cmk; /* colormask (4E0C) */ - struct radeon_state_atom blend_color; /* constant blend color */ - struct radeon_state_atom rop; /* ropcntl */ - struct radeon_state_atom cb; /* colorbuffer (4E28) */ - struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */ - struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */ - struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ - struct radeon_state_atom zs; /* zstencil control (4F00) */ - struct radeon_state_atom zsb; /* zstencil bf */ - struct radeon_state_atom zstencil_format; - struct radeon_state_atom zb; /* z buffer (4F20) */ - struct radeon_state_atom zb_depthclearvalue; /* (4F28) */ - struct radeon_state_atom zb_zmask; /* (4F30) */ - struct radeon_state_atom zb_hiz_offset; /* (4F44) */ - struct radeon_state_atom zb_hiz_pitch; /* (4F54) */ - - struct radeon_state_atom vpi; /* vp instructions */ - struct radeon_state_atom vpp; /* vp parameters */ - struct radeon_state_atom vps; /* vertex point size (?) */ - struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */ - /* 8 texture units */ - /* the state is grouped by function and not by - texture unit. This makes single unit updates - really awkward - we are much better off - updating the whole thing at once */ - struct { - struct radeon_state_atom filter; - struct radeon_state_atom filter_1; - struct radeon_state_atom size; - struct radeon_state_atom format; - struct radeon_state_atom pitch; - struct radeon_state_atom offset; - struct radeon_state_atom chroma_key; - struct radeon_state_atom border_color; - } tex; - struct radeon_state_atom txe; /* tex enable (4104) */ - radeonTexObj *textures[R300_MAX_TEXTURE_UNITS]; -}; - -/** - * State cache - */ - -/* Vertex shader state */ - -#define COLOR_IS_RGBA -#define TAG(x) r300##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG - -struct r300_vertex_program_key { - GLbitfield FpReads; - GLuint FogAttr; - GLuint WPosAttr; -}; - -struct r300_vertex_program { - struct gl_vertex_program *Base; - struct r300_vertex_program *next; - - struct r300_vertex_program_key key; - struct r300_vertex_program_code code; - - GLboolean error; -}; - -struct r300_vertex_program_cont { - /* This is the unmodified vertex program mesa provided us with. - * We need to keep it unchanged because we may need to create another - * hw specific vertex program based on this. - */ - struct gl_vertex_program mesa_program; - /* This is the list of hw specific vertex programs derived from mesa_program */ - struct r300_vertex_program *progs; -}; - - -/** -* Store everything about a fragment program that is needed -* to render with that program. -*/ -struct r300_fragment_program { - GLboolean error; - struct r300_fragment_program *next; - struct r300_fragment_program_external_state state; - - struct rX00_fragment_program_code code; - GLbitfield InputsRead; - - /* attribute that we are sending the WPOS in */ - gl_frag_attrib wpos_attr; - /* attribute that we are sending the fog coordinate in */ - gl_frag_attrib fog_attr; -}; - -struct r300_fragment_program_cont { - /* This is the unmodified fragment program mesa provided us with. - * We need to keep it unchanged because we may need to create another - * hw specific fragment program based on this. - */ - struct gl_fragment_program Base; - /* This is the list of hw specific fragment programs derived from Base */ - struct r300_fragment_program *progs; -}; - - -#define R300_MAX_AOS_ARRAYS 16 - - -/* r300_swtcl.c - */ -struct r300_swtcl_info { - /* - * Offset of the 4UB color data within a hardware (swtcl) vertex. - */ - GLuint coloroffset; - - /** - * Offset of the 3UB specular color data within a hardware (swtcl) vertex. - */ - GLuint specoffset; -}; - -struct r300_vtable { - void (* SetupRSUnit)(struct gl_context *ctx); - void (* SetupFragmentShaderTextures)(struct gl_context *ctx, int *tmu_mappings); - void (* SetupPixelShader)(struct gl_context *ctx); -}; - -struct r300_vertex_buffer { - struct vertex_attribute { - /* generic */ - GLubyte element; - GLuint stride; - GLuint dwords; - GLubyte size; /* number of components */ - GLboolean is_named_bo; - struct radeon_bo *bo; - GLint bo_offset; - - /* hw specific */ - uint32_t data_type:4; - uint32_t dst_loc:5; - uint32_t _signed:1; - uint32_t normalize:1; - uint32_t swizzle:12; - uint32_t write_mask:4; - } attribs[VERT_ATTRIB_MAX]; - - GLubyte num_attribs; -}; - -struct r300_index_buffer { - struct radeon_bo *bo; - int bo_offset; - - GLboolean is_32bit; - GLuint count; -}; - - -/** - * \brief R300 context structure. - */ -struct r300_context { - struct radeon_context radeon; /* parent class, must be first */ - - struct r300_vtable vtbl; - - struct r300_hw_state hw; - - struct r300_vertex_program *selected_vp; - struct r300_fragment_program *selected_fp; - - /* Vertex buffers - */ - GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; - GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - - struct r300_options { - uint32_t conformance_mode:1; - uint32_t hw_tcl_enabled:1; - uint32_t s3tc_force_enabled:1; - uint32_t s3tc_force_disabled:1; - uint32_t stencil_two_side_disabled:1; - } options; - - struct r300_swtcl_info swtcl; - struct r300_vertex_buffer vbuf; - struct r300_index_buffer ind_buf; - - uint32_t fallback; - - struct { - struct r300_vertex_program_code vp_code; - struct rX00_fragment_program_code fp_code; - } blit; - - DECLARE_RENDERINPUTS(render_inputs_bitset); -}; - -#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx)) - -extern void r300DestroyContext(__DRIcontext * driContextPriv); -extern GLboolean r300CreateContext(gl_api api, - const struct gl_config * glVisual, - __DRIcontext * driContextPriv, - void *sharedContextPrivate); - -extern void r300InitShaderFuncs(struct dd_function_table *functions); - -extern void r300InitShaderFunctions(r300ContextPtr r300); - -extern void r300InitDraw(struct gl_context *ctx); - -#define r300PackFloat32 radeonPackFloat32 -#define r300PackFloat24 radeonPackFloat24 - -#endif /* __R300_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c deleted file mode 100644 index 5587c16dd44..00000000000 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ /dev/null @@ -1,759 +0,0 @@ -/************************************************************************** - * - * Copyright 2009 Maciej Cencora - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL THE AUTHOR(S) AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include <stdlib.h> - -#include "main/glheader.h" -#include "main/context.h" -#include "main/state.h" -#include "main/enums.h" -#include "main/simple_list.h" - -#include "r300_reg.h" -#include "r300_context.h" -#include "r300_emit.h" -#include "r300_render.h" -#include "r300_state.h" -#include "r300_tex.h" -#include "r300_cmdbuf.h" - -#include "radeon_buffer_objects.h" -#include "radeon_common_context.h" - -#include "tnl/tnl.h" -#include "tnl/t_vp_build.h" -#include "vbo/vbo_context.h" - - -static int getTypeSize(GLenum type) -{ - switch (type) { - case GL_DOUBLE: - return sizeof(GLdouble); - case GL_HALF_FLOAT: - return sizeof(GLhalfARB); - case GL_FLOAT: - return sizeof(GLfloat); - case GL_INT: - return sizeof(GLint); - case GL_UNSIGNED_INT: - return sizeof(GLuint); - case GL_SHORT: - return sizeof(GLshort); - case GL_UNSIGNED_SHORT: - return sizeof(GLushort); - case GL_BYTE: - return sizeof(GLbyte); - case GL_UNSIGNED_BYTE: - return sizeof(GLubyte); - default: - assert(0); - return 0; - } -} - -static void r300FixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLvoid *src_ptr; - GLuint *out; - int i; - GLboolean mapped_named_bo = GL_FALSE; - - if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) { - ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size, - GL_MAP_READ_BIT, mesa_ind_buf->obj); - mapped_named_bo = GL_TRUE; - assert(mesa_ind_buf->obj->Pointer != NULL); - } - src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); - - radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, - "%s: Fixing index buffer format. type %d\n", - __func__, mesa_ind_buf->type); - - if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) { - GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); - GLubyte *in = (GLubyte *)src_ptr; - - radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4); - radeon_bo_map(r300->ind_buf.bo, 1); - assert(r300->ind_buf.bo->ptr != NULL); - out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); - - for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { - *out++ = in[i] | in[i + 1] << 16; - } - - if (i < mesa_ind_buf->count) { - *out++ = in[i]; - } - radeon_bo_unmap(r300->ind_buf.bo); -#if MESA_BIG_ENDIAN - } else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */ - GLushort *in = (GLushort *)src_ptr; - GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); - - radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, - &r300->ind_buf.bo_offset, size, 4); - - radeon_bo_map(r300->ind_buf.bo, 1); - assert(r300->ind_buf.bo->ptr != NULL); - out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); - - for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { - *out++ = in[i] | in[i + 1] << 16; - } - - if (i < mesa_ind_buf->count) { - *out++ = in[i]; - } - radeon_bo_unmap(r300->ind_buf.bo); -#endif - } - - r300->ind_buf.is_32bit = GL_FALSE; - r300->ind_buf.count = mesa_ind_buf->count; - - if (mapped_named_bo) { - ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj); - } -} - - -static void r300SetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - if (!mesa_ind_buf) { - r300->ind_buf.bo = NULL; - return; - } - radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__); - -#if MESA_BIG_ENDIAN - if (mesa_ind_buf->type == GL_UNSIGNED_INT) { -#else - if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) { -#endif - const GLvoid *src_ptr; - GLvoid *dst_ptr; - GLboolean mapped_named_bo = GL_FALSE; - - if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) { - ctx->Driver.MapBufferRange(ctx, 0, - mesa_ind_buf->obj->Size, - GL_MAP_READ_BIT, - mesa_ind_buf->obj); - assert(mesa_ind_buf->obj->Pointer != NULL); - mapped_named_bo = GL_TRUE; - } - - src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); - - const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type); - - radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4); - - radeon_bo_map(r300->ind_buf.bo, 1); - assert(r300->ind_buf.bo->ptr != NULL); - dst_ptr = ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); - memcpy(dst_ptr, src_ptr, size); - - radeon_bo_unmap(r300->ind_buf.bo); - r300->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT); - r300->ind_buf.count = mesa_ind_buf->count; - - if (mapped_named_bo) { - ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj); - } - } else { - r300FixupIndexBuffer(ctx, mesa_ind_buf); - } -} - -#define CONVERT( TYPE, MACRO ) do { \ - GLuint i, j, sz; \ - sz = input->Size; \ - if (input->Normalized) { \ - for (i = 0; i < count; i++) { \ - const TYPE *in = (TYPE *)src_ptr; \ - for (j = 0; j < sz; j++) { \ - *dst_ptr++ = MACRO(*in); \ - in++; \ - } \ - src_ptr += stride; \ - } \ - } else { \ - for (i = 0; i < count; i++) { \ - const TYPE *in = (TYPE *)src_ptr; \ - for (j = 0; j < sz; j++) { \ - *dst_ptr++ = (GLfloat)(*in); \ - in++; \ - } \ - src_ptr += stride; \ - } \ - } \ -} while (0) - -/** - * Convert attribute data type to float - * If the attribute uses named buffer object replace the bo with newly allocated bo - */ -static void r300ConvertAttrib(struct gl_context *ctx, int count, const struct gl_client_array *input, struct vertex_attribute *attr) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - const GLvoid *src_ptr; - GLboolean mapped_named_bo = GL_FALSE; - GLfloat *dst_ptr; - GLuint stride; - - stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB; - - /* Convert value for first element only */ - if (input->StrideB == 0) - count = 1; - - if (input->BufferObj->Name) { - if (!input->BufferObj->Pointer) { - ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size, - GL_MAP_READ_BIT, input->BufferObj); - mapped_named_bo = GL_TRUE; - } - - src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr); - } else { - src_ptr = input->Ptr; - } - - radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, sizeof(GLfloat) * input->Size * count, 32); - radeon_bo_map(attr->bo, 1); - dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset); - - radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, - "%s: Converting vertex attributes, attribute data format %x," - "stride %d, components %d\n" - , __FUNCTION__, input->Type - , stride, input->Size); - - assert(src_ptr != NULL); - - switch (input->Type) { - case GL_DOUBLE: - CONVERT(GLdouble, (GLfloat)); - break; - case GL_UNSIGNED_INT: - CONVERT(GLuint, UINT_TO_FLOAT); - break; - case GL_INT: - CONVERT(GLint, INT_TO_FLOAT); - break; - case GL_UNSIGNED_SHORT: - CONVERT(GLushort, USHORT_TO_FLOAT); - break; - case GL_SHORT: - CONVERT(GLshort, SHORT_TO_FLOAT); - break; - case GL_UNSIGNED_BYTE: - assert(input->Format != GL_BGRA); - CONVERT(GLubyte, UBYTE_TO_FLOAT); - break; - case GL_BYTE: - CONVERT(GLbyte, BYTE_TO_FLOAT); - break; - default: - assert(0); - break; - } - - radeon_bo_unmap(attr->bo); - if (mapped_named_bo) { - ctx->Driver.UnmapBuffer(ctx, input->BufferObj); - } -} - -static void r300AlignDataToDword(struct gl_context *ctx, const struct gl_client_array *input, int count, struct vertex_attribute *attr) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - const int dst_stride = (input->StrideB + 3) & ~3; - const int size = getTypeSize(input->Type) * input->Size * count; - GLboolean mapped_named_bo = GL_FALSE; - - radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, size, 32); - - radeon_bo_map(attr->bo, 1); - - if (!input->BufferObj->Pointer) { - ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size, - GL_MAP_READ_BIT, input->BufferObj); - mapped_named_bo = GL_TRUE; - } - - radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s. Vertex alignment doesn't match hw requirements.\n", __func__); - - { - GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr); - GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset); - int i; - - for (i = 0; i < count; ++i) { - memcpy(dst_ptr, src_ptr, input->StrideB); - src_ptr += input->StrideB; - dst_ptr += dst_stride; - } - } - - if (mapped_named_bo) { - ctx->Driver.UnmapBuffer(ctx, input->BufferObj); - } - - radeon_bo_unmap(attr->bo); - attr->stride = dst_stride; -} - -static void r300TranslateAttrib(struct gl_context *ctx, GLuint attr, int count, const struct gl_client_array *input) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_vertex_buffer *vbuf = &r300->vbuf; - struct vertex_attribute r300_attr = { 0 }; - GLenum type; - GLuint stride; - - radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__); - stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB; - - if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || -#if MESA_BIG_ENDIAN - getTypeSize(input->Type) != 4 || -#endif - stride < 4) { - - type = GL_FLOAT; - - if (input->StrideB == 0) { - r300_attr.stride = 0; - } else { - r300_attr.stride = sizeof(GLfloat) * input->Size; - } - r300_attr.dwords = input->Size; - r300_attr.is_named_bo = GL_FALSE; - } else { - type = input->Type; - r300_attr.dwords = (getTypeSize(type) * input->Size + 3)/ 4; - if (!input->BufferObj->Name) { - - if (input->StrideB == 0) { - r300_attr.stride = 0; - } else { - r300_attr.stride = (getTypeSize(type) * input->Size + 3) & ~3; - } - - r300_attr.is_named_bo = GL_FALSE; - } - } - - r300_attr.size = input->Size; - r300_attr.element = attr; - r300_attr.dst_loc = vbuf->num_attribs; - - switch (type) { - case GL_FLOAT: - switch (input->Size) { - case 1: r300_attr.data_type = R300_DATA_TYPE_FLOAT_1; break; - case 2: r300_attr.data_type = R300_DATA_TYPE_FLOAT_2; break; - case 3: r300_attr.data_type = R300_DATA_TYPE_FLOAT_3; break; - case 4: r300_attr.data_type = R300_DATA_TYPE_FLOAT_4; break; - } - r300_attr._signed = 0; - r300_attr.normalize = 0; - break; - case GL_HALF_FLOAT: - switch (input->Size) { - case 1: - case 2: - r300_attr.data_type = R300_DATA_TYPE_FLT16_2; - break; - case 3: - case 4: - r300_attr.data_type = R300_DATA_TYPE_FLT16_4; - break; - } - break; - case GL_SHORT: - r300_attr._signed = 1; - r300_attr.normalize = input->Normalized; - switch (input->Size) { - case 1: - case 2: - r300_attr.data_type = R300_DATA_TYPE_SHORT_2; - break; - case 3: - case 4: - r300_attr.data_type = R300_DATA_TYPE_SHORT_4; - break; - } - break; - case GL_BYTE: - r300_attr._signed = 1; - r300_attr.normalize = input->Normalized; - r300_attr.data_type = R300_DATA_TYPE_BYTE; - break; - case GL_UNSIGNED_SHORT: - r300_attr._signed = 0; - r300_attr.normalize = input->Normalized; - switch (input->Size) { - case 1: - case 2: - r300_attr.data_type = R300_DATA_TYPE_SHORT_2; - break; - case 3: - case 4: - r300_attr.data_type = R300_DATA_TYPE_SHORT_4; - break; - } - break; - case GL_UNSIGNED_BYTE: - r300_attr._signed = 0; - r300_attr.normalize = input->Normalized; - if (input->Format == GL_BGRA) - r300_attr.data_type = R300_DATA_TYPE_D3DCOLOR; - else - r300_attr.data_type = R300_DATA_TYPE_BYTE; - break; - - default: - case GL_DOUBLE: - case GL_INT: - case GL_UNSIGNED_INT: - assert(0); - break; - } - - switch (input->Size) { - case 4: - r300_attr.swizzle = SWIZZLE_XYZW; - break; - case 3: - r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - break; - case 2: - r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); - break; - case 1: - r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); - break; - } - - r300_attr.write_mask = MASK_XYZW; - - vbuf->attribs[vbuf->num_attribs] = r300_attr; - ++vbuf->num_attribs; -} - -static void r300SetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_vertex_buffer *vbuf = &r300->vbuf; - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__); - { - int i, tmp; - - tmp = r300->selected_vp->code.InputsRead; - i = 0; - vbuf->num_attribs = 0; - while (tmp) { - /* find first enabled bit */ - while (!(tmp & 1)) { - tmp >>= 1; - ++i; - } - - r300TranslateAttrib(ctx, i, count, arrays[i]); - - tmp >>= 1; - ++i; - } - } - - r300SwitchFallback(ctx, R300_FALLBACK_AOS_LIMIT, vbuf->num_attribs > R300_MAX_AOS_ARRAYS); - if (r300->fallback) - return; -} - -static void r300AllocDmaRegions(struct gl_context *ctx, const struct gl_client_array *input[], int count) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_vertex_buffer *vbuf = &r300->vbuf; - GLuint stride; - int ret; - int i, index; - radeon_print(RADEON_RENDER, RADEON_VERBOSE, - "%s: count %d num_attribs %d\n", - __func__, count, vbuf->num_attribs); - - for (index = 0; index < vbuf->num_attribs; index++) { - struct radeon_aos *aos = &r300->radeon.tcl.aos[index]; - i = vbuf->attribs[index].element; - - stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB; - - if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT || -#if MESA_BIG_ENDIAN - getTypeSize(input[i]->Type) != 4 || -#endif - stride < 4) { - - r300ConvertAttrib(ctx, count, input[i], &vbuf->attribs[index]); - } else { - if (input[i]->BufferObj->Name) { - if (stride % 4 != 0 || (intptr_t)input[i]->Ptr % 4 != 0) { - r300AlignDataToDword(ctx, input[i], count, &vbuf->attribs[index]); - vbuf->attribs[index].is_named_bo = GL_FALSE; - } else { - vbuf->attribs[index].stride = input[i]->StrideB; - vbuf->attribs[index].bo_offset = (intptr_t) input[i]->Ptr; - vbuf->attribs[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo; - vbuf->attribs[index].is_named_bo = GL_TRUE; - } - } else { - - int size; - int local_count = count; - uint32_t *dst; - - if (input[i]->StrideB == 0) { - size = getTypeSize(input[i]->Type) * input[i]->Size; - local_count = 1; - } else { - size = getTypeSize(input[i]->Type) * input[i]->Size * local_count; - } - - radeonAllocDmaRegion(&r300->radeon, &vbuf->attribs[index].bo, &vbuf->attribs[index].bo_offset, size, 32); - radeon_bo_map(vbuf->attribs[index].bo, 1); - assert(vbuf->attribs[index].bo->ptr != NULL); - dst = (uint32_t *)ADD_POINTERS(vbuf->attribs[index].bo->ptr, vbuf->attribs[index].bo_offset); - switch (vbuf->attribs[index].dwords) { - case 1: radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; - case 2: radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; - case 3: radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; - case 4: radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; - default: assert(0); break; - } - radeon_bo_unmap(vbuf->attribs[index].bo); - - } - } - - aos->count = vbuf->attribs[index].stride == 0 ? 1 : count; - aos->stride = vbuf->attribs[index].stride / sizeof(float); - aos->components = vbuf->attribs[index].dwords; - aos->bo = vbuf->attribs[index].bo; - aos->offset = vbuf->attribs[index].bo_offset; - - if (vbuf->attribs[index].is_named_bo) { - radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs, r300->vbuf.attribs[index].bo, RADEON_GEM_DOMAIN_GTT, 0); - } - } - - r300->radeon.tcl.aos_count = vbuf->num_attribs; - ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, first_elem(&r300->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0); - r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, ret); - -} - -static void r300FreeData(struct gl_context *ctx) -{ - /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo - * to prevent double unref in radeonReleaseArrays - * called during context destroy - */ - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__); - r300ContextPtr r300 = R300_CONTEXT(ctx); - { - int i; - - for (i = 0; i < r300->vbuf.num_attribs; i++) { - if (!r300->vbuf.attribs[i].is_named_bo) { - radeon_bo_unref(r300->vbuf.attribs[i].bo); - } - r300->radeon.tcl.aos[i].bo = NULL; - } - } - - { - if (r300->ind_buf.bo != NULL) { - radeon_bo_unref(r300->ind_buf.bo); - } - } -} - -static GLuint r300PredictTryDrawPrimsSize(struct gl_context *ctx, - GLuint nr_prims, const struct _mesa_prim *prim) -{ - struct r300_context *r300 = R300_CONTEXT(ctx); - struct r300_vertex_buffer *vbuf = &r300->vbuf; - GLboolean flushed; - GLuint dwords; - GLuint state_size; - int i; - GLuint extra_prims = 0; - - /* Check for primitive splitting. */ - for (i = 0; i < nr_prims; ++i) { - const GLuint num_verts = r300NumVerts(r300, prim[i].count, prim[i].mode); - extra_prims += num_verts/(65535 - 32); - } - nr_prims += extra_prims; - - dwords = 2*CACHE_FLUSH_BUFSZ; - dwords += PRE_EMIT_STATE_BUFSZ; - dwords += (AOS_BUFSZ(vbuf->num_attribs) - + SCISSORS_BUFSZ*2 - + FIREAOS_BUFSZ )*nr_prims; - - state_size = radeonCountStateEmitSize(&r300->radeon); - flushed = rcommonEnsureCmdBufSpace(&r300->radeon, - dwords + state_size, - __FUNCTION__); - if (flushed) - dwords += radeonCountStateEmitSize(&r300->radeon); - else - dwords += state_size; - - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); - return dwords; -} - -static GLboolean r300TryDrawPrims(struct gl_context *ctx, - const struct gl_client_array *arrays[], - const struct _mesa_prim *prim, - GLuint nr_prims, - const struct _mesa_index_buffer *ib, - GLuint min_index, - GLuint max_index ) -{ - struct r300_context *r300 = R300_CONTEXT(ctx); - GLuint i; - - radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: %u (%d-%d) cs begin at %d\n", - __FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw ); - - if (ctx->NewState) - _mesa_update_state( ctx ); - - if (r300->options.hw_tcl_enabled) - _tnl_UpdateFixedFunctionProgram(ctx); - - r300UpdateShaders(r300); - - r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx)); - - r300SetVertexFormat(ctx, arrays, max_index + 1); - - if (r300->fallback) - return GL_FALSE; - - r300SetupVAP(ctx, r300->selected_vp->code.InputsRead, r300->selected_vp->code.OutputsWritten); - - r300UpdateShaderStates(r300); - - /* ensure we have the cmd buf space in advance to cover - * the state + DMA AOS pointers */ - GLuint emit_end = r300PredictTryDrawPrimsSize(ctx, nr_prims, prim) - + r300->radeon.cmdbuf.cs->cdw; - - r300SetupIndexBuffer(ctx, ib); - - r300AllocDmaRegions(ctx, arrays, max_index + 1); - - if (r300->fallback) - return GL_FALSE; - - r300EmitCacheFlush(r300); - radeonEmitState(&r300->radeon); - - for (i = 0; i < nr_prims; ++i) { - r300RunRenderPrimitive(ctx, prim[i].start, prim[i].start + prim[i].count, prim[i].mode); - } - - r300EmitCacheFlush(r300); - - r300FreeData(ctx); - - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: %u (%d-%d) cs ending at %d\n", - __FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw ); - - if (emit_end < r300->radeon.cmdbuf.cs->cdw) - WARN_ONCE("Rendering was %d commands larger than predicted size." - " We might overflow command buffer.\n", r300->radeon.cmdbuf.cs->cdw - emit_end); - - return GL_TRUE; -} - -static void r300DrawPrims(struct gl_context *ctx, - const struct gl_client_array *arrays[], - const struct _mesa_prim *prim, - GLuint nr_prims, - const struct _mesa_index_buffer *ib, - GLboolean index_bounds_valid, - GLuint min_index, - GLuint max_index) -{ - GLboolean retval; - struct r300_context *r300 = R300_CONTEXT(ctx); - radeonContextPtr radeon = &r300->radeon; - - radeon_prepare_render(radeon); - - /* This check should get folded into just the places that - * min/max index are really needed. - */ - if (!index_bounds_valid) { - vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index); - } - - if (min_index) { - radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, - "%s: Rebasing primitives. %p nr_prims %d min_index %u max_index %u\n", - __func__, prim, nr_prims, min_index, max_index); - vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r300DrawPrims ); - return; - } - - /* Make an attempt at drawing */ - retval = r300TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); - - /* If failed run tnl pipeline - it should take care of fallbacks */ - if (!retval) - _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); -} - -void r300InitDraw(struct gl_context *ctx) -{ - struct vbo_context *vbo = vbo_context(ctx); - - vbo->draw_prims = r300DrawPrims; -} diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c deleted file mode 100644 index f392006cedc..00000000000 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ /dev/null @@ -1,135 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Keith Whitwell <[email protected]> - * \author Maciej Cencora <[email protected]> - */ - -#include "main/glheader.h" -#include "main/mtypes.h" -#include "main/colormac.h" -#include "main/imports.h" -#include "main/macros.h" - -#include "swrast_setup/swrast_setup.h" -#include "tnl/tnl.h" -#include "tnl/t_context.h" - -#include "r300_context.h" -#include "r300_emit.h" - - -GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead) -{ - /* No idea what this value means. I have seen other values written to - * this register... */ - return 0x5555; -} - -GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead) -{ - GLuint i, vic_1 = 0; - - if (InputsRead & (1 << VERT_ATTRIB_POS)) - vic_1 |= R300_INPUT_CNTL_POS; - - if (InputsRead & (1 << VERT_ATTRIB_NORMAL)) - vic_1 |= R300_INPUT_CNTL_NORMAL; - - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - vic_1 |= R300_INPUT_CNTL_COLOR; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) - if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) { - vic_1 |= R300_INPUT_CNTL_TC0 << i; - } - - return vic_1; -} - -GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes) -{ - GLuint ret = 0; - - if (vp_writes & (1 << VERT_RESULT_HPOS)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; - - if (vp_writes & (1 << VERT_RESULT_COL0)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT; - - if (vp_writes & (1 << VERT_RESULT_COL1)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; - - /* Two sided lighting works only if all 4 colors are written */ - if (vp_writes & (1 << VERT_RESULT_BFC0) || vp_writes & (1 << VERT_RESULT_BFC1)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; - - if (vp_writes & (1 << VERT_RESULT_PSIZ)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; - - return ret; -} - -GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes) -{ - GLuint i, ret = 0, first_free_texcoord = 0; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (vp_writes & (1 << (VERT_RESULT_TEX0 + i))) { - ret |= (4 << (3 * first_free_texcoord)); - ++first_free_texcoord; - } - } - - if (first_free_texcoord > 8) { - fprintf(stderr, "\tout of free texcoords\n"); - exit(-1); - } - - return ret; -} - -void r300EmitCacheFlush(r300ContextPtr rmesa) -{ - BATCH_LOCALS(&rmesa->radeon); - - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, - R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | - R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT, - R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | - R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); - END_BATCH(); - COMMIT_BATCH(); -} diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h deleted file mode 100644 index 8911ab77283..00000000000 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (C) 2005 Vladimir Dergachev. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Vladimir Dergachev <[email protected]> - * Nicolai Haehnle <[email protected]> - * Aapo Tahkola <[email protected]> - * Ben Skeggs <[email protected]> - * Jerome Glisse <[email protected]> - */ - -/* This files defines functions for accessing R300 hardware. - */ -#ifndef __R300_EMIT_H__ -#define __R300_EMIT_H__ - -#include "main/glheader.h" -#include "r300_context.h" -#include "r300_cmdbuf.h" - -static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, - int reg, int count) -{ - if (!rscrn->kernel_mm) { - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.packet0.cmd_type = R300_CMD_PACKET0; - cmd.packet0.count = count; - cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8; - cmd.packet0.reglo = ((unsigned int)reg & 0x00FF); - - return cmd.u; - } - if (count) { - return CP_PACKET0(reg, count - 1); - } - return CP_PACKET2; -} - -static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.vpu.cmd_type = R300_CMD_VPU; - cmd.vpu.count = count; - cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8; - cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, - int addr, int count, int type, int clamp) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.r500fp.cmd_type = R300_CMD_R500FP; - cmd.r500fp.count = count; - cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8; - cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0; - cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0; - cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.packet3.cmd_type = R300_CMD_PACKET3; - cmd.packet3.packet = packet; - - return cmd.u; -} - -static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, - unsigned short count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - - cmd.delay.cmd_type = R300_CMD_CP_DELAY; - cmd.delay.count = count; - - return cmd.u; -} - -static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, - unsigned char flags) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.wait.cmd_type = R300_CMD_WAIT; - cmd.wait.flags = flags; - - return cmd.u; -} - -static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.header.cmd_type = R300_CMD_END3D; - - return cmd.u; -} - -/** - * Write the header of a packet3 to the command buffer. - * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. - */ -#define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ - R300_CMD_PACKET3_RAW)); \ - } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ - OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ - } while(0) - -/** - * Must be sent to switch to 2d commands - */ -void static INLINE end_3d(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdpacify(radeon->radeonScreen)); - END_BATCH(); - } -} - -void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) -{ - BATCH_LOCALS(&rmesa->radeon); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } -} - -void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) -{ - BATCH_LOCALS(radeon); - uint32_t wait_until; - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } -} - -extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); -extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); - -extern void r300EmitCacheFlush(r300ContextPtr rmesa); - -extern GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead); -extern GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead); -extern GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes); -extern GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes); - -#endif diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c deleted file mode 100644 index f0d960dca54..00000000000 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/** - * \file - * - * Fragment program compiler. Perform transformations on the intermediate - * representation until the program is in a form where we can translate - * it more or less directly into machine-readable form. - * - * \author Ben Skeggs <[email protected]> - * \author Jerome Glisse <[email protected]> - */ - -#include "r300_fragprog_common.h" - -#include "program/prog_print.h" - -#include "compiler/radeon_compiler.h" - -#include "radeon_mesa_to_rc.h" - - -static GLuint build_dts(GLuint depthmode) -{ - switch(depthmode) { - default: - case GL_LUMINANCE: return RC_SWIZZLE_XYZZ; - case GL_INTENSITY: return RC_SWIZZLE_XYZW; - case GL_ALPHA: return RC_SWIZZLE_WWWW; - } -} - -static GLuint build_func(GLuint comparefunc) -{ - return comparefunc - GL_NEVER; -} - -/** - * Collect all external state that is relevant for compiling the given - * fragment program. - */ -static void build_state( - r300ContextPtr r300, - struct gl_fragment_program *fp, - struct r300_fragment_program_external_state *state) -{ - int unit; - - memset(state, 0, sizeof(*state)); - - for(unit = 0; unit < 16; ++unit) { - if (fp->Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; - - state->unit[unit].texture_swizzle = build_dts(tex->Sampler.DepthMode); - state->unit[unit].texture_compare_func = build_func(tex->Sampler.CompareFunc); - } - } -} - - -/** - * Transform the program to support fragment.position. - * - * Introduce a small fragment at the start of the program that will be - * the only code that directly reads the FRAG_ATTRIB_WPOS input. - * All other code pieces that reference that input will be rewritten - * to read from a newly allocated temporary. - * - */ -static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp) -{ - int i; - - fp->wpos_attr = FRAG_ATTRIB_MAX; - if (!(compiler->Base.Program.InputsRead & FRAG_BIT_WPOS)) { - return; - } - - for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i) - { - if (!(compiler->Base.Program.InputsRead & (1 << i))) { - fp->wpos_attr = i; - break; - } - } - - /* No free texcoord found, fall-back to software rendering */ - if (fp->wpos_attr == FRAG_ATTRIB_MAX) - { - compiler->Base.Error = 1; - return; - } - - rc_transform_fragment_wpos(&compiler->Base, FRAG_ATTRIB_WPOS, fp->wpos_attr, GL_FALSE); -} - -/** - * Rewrite fragment.fogcoord to use a texture coordinate slot. - * Note that fogcoord is forced into an X001 pattern, and this enforcement - * is done here. - * - * See also the counterpart rewriting for vertex programs. - */ -static void rewriteFog(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp) -{ - struct rc_src_register src; - int i; - - fp->fog_attr = FRAG_ATTRIB_MAX; - if (!(compiler->Base.Program.InputsRead & FRAG_BIT_FOGC)) { - return; - } - - for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i) - { - if (!(compiler->Base.Program.InputsRead & (1 << i))) { - fp->fog_attr = i; - break; - } - } - - /* No free texcoord found, fall-back to software rendering */ - if (fp->fog_attr == FRAG_ATTRIB_MAX) - { - compiler->Base.Error = 1; - return; - } - - memset(&src, 0, sizeof(src)); - src.File = RC_FILE_INPUT; - src.Index = fp->fog_attr; - src.Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); - rc_move_input(&compiler->Base, FRAG_ATTRIB_FOGC, src); -} - - -/** - * Reserve hardware temporary registers for the program inputs. - * - * @note This allocation is performed explicitly, because the order of inputs - * is determined by the RS hardware. - */ -static void allocate_hw_inputs( - struct r300_fragment_program_compiler * c, - void (*allocate)(void * data, unsigned input, unsigned hwreg), - void * mydata) -{ - GLuint InputsRead = c->Base.Program.InputsRead; - int i; - GLuint hwindex = 0; - - /* Primary colour */ - if (InputsRead & FRAG_BIT_COL0) - allocate(mydata, FRAG_ATTRIB_COL0, hwindex++); - InputsRead &= ~FRAG_BIT_COL0; - - /* Secondary color */ - if (InputsRead & FRAG_BIT_COL1) - allocate(mydata, FRAG_ATTRIB_COL1, hwindex++); - InputsRead &= ~FRAG_BIT_COL1; - - /* Texcoords */ - for (i = 0; i < 8; i++) { - if (InputsRead & (FRAG_BIT_TEX0 << i)) - allocate(mydata, FRAG_ATTRIB_TEX0+i, hwindex++); - } - InputsRead &= ~FRAG_BITS_TEX_ANY; - - /* Fogcoords treated as a texcoord */ - if (InputsRead & FRAG_BIT_FOGC) - allocate(mydata, FRAG_ATTRIB_FOGC, hwindex++); - InputsRead &= ~FRAG_BIT_FOGC; - - /* fragment position treated as a texcoord */ - if (InputsRead & FRAG_BIT_WPOS) - allocate(mydata, FRAG_ATTRIB_WPOS, hwindex++); - InputsRead &= ~FRAG_BIT_WPOS; - - /* Anything else */ - if (InputsRead) - rc_error(&c->Base, "Don't know how to handle inputs 0x%x\n", InputsRead); -} - - -static void translate_fragment_program(struct gl_context *ctx, struct r300_fragment_program_cont *cont, struct r300_fragment_program *fp) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_fragment_program_compiler compiler; - - memset(&compiler, 0, sizeof(compiler)); - rc_init(&compiler.Base); - compiler.Base.Debug = (RADEON_DEBUG & RADEON_PIXEL) ? GL_TRUE : GL_FALSE; - - compiler.code = &fp->code; - compiler.state = fp->state; - compiler.enable_shadow_ambient = GL_TRUE; - compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ? GL_TRUE : GL_FALSE; - compiler.Base.disable_optimizations = 0; - compiler.Base.has_half_swizzles = 1; - compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32; - compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32; - compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64; - compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32; - compiler.OutputDepth = FRAG_RESULT_DEPTH; - memset(compiler.OutputColor, 0, 4 * sizeof(unsigned)); - compiler.OutputColor[0] = FRAG_RESULT_COLOR; - compiler.AllocateHwInputs = &allocate_hw_inputs; - - if (compiler.Base.Debug) { - fflush(stderr); - printf("Fragment Program: Initial program:\n"); - _mesa_print_program(&cont->Base.Base); - fflush(stderr); - } - - radeon_mesa_to_rc_program(&compiler.Base, &cont->Base.Base); - - insert_WPOS_trailer(&compiler, fp); - - rewriteFog(&compiler, fp); - - r3xx_compile_fragment_program(&compiler); - - if (compiler.Base.is_r500) { - /* We need to support the non-KMS DRM interface, which - * artificially limits the number of instructions and - * constants which are available to us. - * - * See also the comment in r300_context.c where we - * set the MAX_NATIVE_xxx values. - */ - if (fp->code.code.r500.inst_end >= 255 || fp->code.constants.Count > 255) - rc_error(&compiler.Base, "Program is too big (upgrade to r300g to avoid this limitation).\n"); - } - - fp->error = compiler.Base.Error; - - fp->InputsRead = compiler.Base.Program.InputsRead; - - /* Clear the fog/wpos_attr if code accessing these - * attributes has been removed during compilation - */ - if (fp->fog_attr != FRAG_ATTRIB_MAX) { - if (!(fp->InputsRead & (1 << fp->fog_attr))) - fp->fog_attr = FRAG_ATTRIB_MAX; - } - - if (fp->wpos_attr != FRAG_ATTRIB_MAX) { - if (!(fp->InputsRead & (1 << fp->wpos_attr))) - fp->wpos_attr = FRAG_ATTRIB_MAX; - } - - rc_destroy(&compiler.Base); -} - -struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_fragment_program_cont *fp_list; - struct r300_fragment_program *fp; - struct r300_fragment_program_external_state state; - - fp_list = (struct r300_fragment_program_cont *)ctx->FragmentProgram._Current; - build_state(r300, ctx->FragmentProgram._Current, &state); - - fp = fp_list->progs; - while (fp) { - if (memcmp(&fp->state, &state, sizeof(state)) == 0) { - return r300->selected_fp = fp; - } - fp = fp->next; - } - - fp = calloc(1, sizeof(struct r300_fragment_program)); - - fp->state = state; - - fp->next = fp_list->progs; - fp_list->progs = fp; - - translate_fragment_program(ctx, fp_list, fp); - - return r300->selected_fp = fp; -} diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.h b/src/mesa/drivers/dri/r300/r300_fragprog_common.h deleted file mode 100644 index cfa5acf4330..00000000000 --- a/src/mesa/drivers/dri/r300/r300_fragprog_common.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __R300_FRAGPROG_COMMON_H_ -#define __R300_FRAGPROG_COMMON_H_ - -#include "main/mtypes.h" - -#include "r300_context.h" - -struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx); - -#endif diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h deleted file mode 100644 index 8980bd3dde1..00000000000 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ /dev/null @@ -1,3378 +0,0 @@ -/************************************************************************** - -Copyright (C) 2004-2005 Nicolai Haehnle et al. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* *INDENT-OFF* */ - -#ifndef _R300_REG_H -#define _R300_REG_H - -#define R300_MC_INIT_MISC_LAT_TIMER 0x180 -# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 - - -#define R300_MC_INIT_GFX_LAT_TIMER 0x154 -# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 - -/* - * This file contains registers and constants for the R300. They have been - * found mostly by examining command buffers captured using glxtest, as well - * as by extrapolating some known registers and constants from the R200. - * I am fairly certain that they are correct unless stated otherwise - * in comments. - */ - -#define R300_SE_VPORT_XSCALE 0x1D98 -#define R300_SE_VPORT_XOFFSET 0x1D9C -#define R300_SE_VPORT_YSCALE 0x1DA0 -#define R300_SE_VPORT_YOFFSET 0x1DA4 -#define R300_SE_VPORT_ZSCALE 0x1DA8 -#define R300_SE_VPORT_ZOFFSET 0x1DAC - -#define R300_VAP_PORT_IDX0 0x2040 -/* - * Vertex Array Processing (VAP) Control - */ -#define R300_VAP_CNTL 0x2080 -# define R300_PVS_NUM_SLOTS_SHIFT 0 -# define R300_PVS_NUM_CNTLRS_SHIFT 4 -# define R300_PVS_NUM_FPUS_SHIFT 8 -# define R300_VF_MAX_VTX_NUM_SHIFT 18 -# define R300_GL_CLIP_SPACE_DEF (0 << 22) -# define R300_DX_CLIP_SPACE_DEF (1 << 22) -# define R500_TCL_STATE_OPTIMIZATION (1 << 23) - -/* This register is written directly and also starts data section - * in many 3d CP_PACKET3's - */ -#define R300_VAP_VF_CNTL 0x2084 -# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 -# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) -# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) -# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) -# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) -# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) -# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) - -# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 - /* State based - direct writes to registers trigger vertex - generation */ -# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) - - /* I don't think I saw these three used.. */ -# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 -# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 -# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 - - /* index size - when not set the indices are assumed to be 16 bit */ -# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) - /* number of vertices */ -# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 - -#define R500_VAP_INDEX_OFFSET 0x208c - -#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 -# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) -# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) - -#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 - /* each of the following is 3 bits wide, specifies number - of components */ -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 -# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0 -# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1 -# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2 -# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3 -# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4 - -#define R300_SE_VTE_CNTL 0x20b0 -# define R300_VPORT_X_SCALE_ENA (1 << 0) -# define R300_VPORT_X_OFFSET_ENA (1 << 1) -# define R300_VPORT_Y_SCALE_ENA (1 << 2) -# define R300_VPORT_Y_OFFSET_ENA (1 << 3) -# define R300_VPORT_Z_SCALE_ENA (1 << 4) -# define R300_VPORT_Z_OFFSET_ENA (1 << 5) -# define R300_VTX_XY_FMT (1 << 8) -# define R300_VTX_Z_FMT (1 << 9) -# define R300_VTX_W0_FMT (1 << 10) -# define R300_SERIAL_PROC_ENA (1 << 11) - -/* BEGIN: Vertex data assembly - lots of uncertainties */ - -/* gap */ - -/* Maximum Vertex Indx Clamp */ -#define R300_VAP_VF_MAX_VTX_INDX 0x2134 -/* Minimum Vertex Indx Clamp */ -#define R300_VAP_VF_MIN_VTX_INDX 0x2138 - -/** Vertex assembler/processor control status */ -#define R300_VAP_CNTL_STATUS 0x2140 -/* No swap at all (default) */ -# define R300_VC_NO_SWAP (0 << 0) -/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */ -# define R300_VC_16BIT_SWAP (1 << 0) -/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */ -# define R300_VC_32BIT_SWAP (2 << 0) -/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */ -# define R300_VC_HALF_DWORD_SWAP (3 << 0) -/* The TCL engine will not be used (as it is logically or even physically removed) */ -# define R300_VAP_TCL_BYPASS (1 << 8) -/* Read only flag if TCL engine is busy. */ -# define R300_VAP_PVS_BUSY (1 << 11) -/* TODO: gap for MAX_MPS */ -/* Read only flag if the vertex store is busy. */ -# define R300_VAP_VS_BUSY (1 << 24) -/* Read only flag if the reciprocal engine is busy. */ -# define R300_VAP_RCP_BUSY (1 << 25) -/* Read only flag if the viewport transform engine is busy. */ -# define R300_VAP_VTE_BUSY (1 << 26) -/* Read only flag if the memory interface unit is busy. */ -# define R300_VAP_MUI_BUSY (1 << 27) -/* Read only flag if the vertex cache is busy. */ -# define R300_VAP_VC_BUSY (1 << 28) -/* Read only flag if the vertex fetcher is busy. */ -# define R300_VAP_VF_BUSY (1 << 29) -/* Read only flag if the register pipeline is busy. */ -# define R300_VAP_REGPIPE_BUSY (1 << 30) -/* Read only flag if the VAP engine is busy. */ -# define R300_VAP_VAP_BUSY (1 << 31) - -/* gap */ - -/* Where do we get our vertex data? - * - * Vertex data either comes either from immediate mode registers or from - * vertex arrays. - * There appears to be no mixed mode (though we can force the pitch of - * vertex arrays to 0, effectively reusing the same element over and over - * again). - * - * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure - * if these registers influence vertex array processing. - * - * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. - * - * In both cases, vertex attributes are then passed through INPUT_ROUTE. - * - * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data - * into the vertex processor's input registers. - * The first word routes the first input, the second word the second, etc. - * The corresponding input is routed into the register with the given index. - * The list is ended by a word with INPUT_ROUTE_END set. - * - * Always set COMPONENTS_4 in immediate mode. - */ - -#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 -# define R300_DATA_TYPE_0_SHIFT 0 -# define R300_DATA_TYPE_FLOAT_1 0 -# define R300_DATA_TYPE_FLOAT_2 1 -# define R300_DATA_TYPE_FLOAT_3 2 -# define R300_DATA_TYPE_FLOAT_4 3 -# define R300_DATA_TYPE_BYTE 4 -# define R300_DATA_TYPE_D3DCOLOR 5 -# define R300_DATA_TYPE_SHORT_2 6 -# define R300_DATA_TYPE_SHORT_4 7 -# define R300_DATA_TYPE_VECTOR_3_TTT 8 -# define R300_DATA_TYPE_VECTOR_3_EET 9 -# define R300_DATA_TYPE_FLT16_2 11 -# define R300_DATA_TYPE_FLT16_4 12 - -# define R300_SKIP_DWORDS_SHIFT 4 -# define R300_DST_VEC_LOC_SHIFT 8 -# define R300_LAST_VEC (1 << 13) -# define R300_SIGNED (1 << 14) -# define R300_NORMALIZE (1 << 15) -# define R300_DATA_TYPE_1_SHIFT 16 -#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 -#define R300_VAP_PROG_STREAM_CNTL_2 0x2158 -#define R300_VAP_PROG_STREAM_CNTL_3 0x215C -#define R300_VAP_PROG_STREAM_CNTL_4 0x2160 -#define R300_VAP_PROG_STREAM_CNTL_5 0x2164 -#define R300_VAP_PROG_STREAM_CNTL_6 0x2168 -#define R300_VAP_PROG_STREAM_CNTL_7 0x216C -/* gap */ - -/* Notes: - * - always set up to produce at least two attributes: - * if vertex program uses only position, fglrx will set normal, too - * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. - */ -#define R300_VAP_VTX_STATE_CNTL 0x2180 -# define R300_COLOR_0_ASSEMBLY_SHIFT 0 -# define R300_SEL_COLOR 0 -# define R300_SEL_USER_COLOR_0 1 -# define R300_SEL_USER_COLOR_1 2 -# define R300_COLOR_1_ASSEMBLY_SHIFT 2 -# define R300_COLOR_2_ASSEMBLY_SHIFT 4 -# define R300_COLOR_3_ASSEMBLY_SHIFT 6 -# define R300_COLOR_4_ASSEMBLY_SHIFT 8 -# define R300_COLOR_5_ASSEMBLY_SHIFT 10 -# define R300_COLOR_6_ASSEMBLY_SHIFT 12 -# define R300_COLOR_7_ASSEMBLY_SHIFT 14 -# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16) - -/* - * Each bit in this field applies to the corresponding vector in the VSM - * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit - * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream. - */ -#define R300_VAP_VSM_VTX_ASSM 0x2184 -# define R300_INPUT_CNTL_POS 0x00000001 -# define R300_INPUT_CNTL_NORMAL 0x00000002 -# define R300_INPUT_CNTL_COLOR 0x00000004 -# define R300_INPUT_CNTL_TC0 0x00000400 -# define R300_INPUT_CNTL_TC1 0x00000800 -# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ -# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ -# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ -# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ -# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ -# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ - -/* Programmable Stream Control Signed Normalize Control */ -#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc -# define SGN_NORM_ZERO 0 -# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1 -# define SGN_NORM_NO_ZERO 2 - -/* gap */ - -/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 - * are set to a swizzling bit pattern, other words are 0. - * - * In immediate mode, the pattern is always set to xyzw. In vertex array - * mode, the swizzling pattern is e.g. used to set zw components in texture - * coordinates with only tweo components. - */ -#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 -# define R300_SWIZZLE0_SHIFT 0 -# define R300_SWIZZLE_SELECT_X_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_SHIFT 9 - -# define R300_SWIZZLE_SELECT_X 0 -# define R300_SWIZZLE_SELECT_Y 1 -# define R300_SWIZZLE_SELECT_Z 2 -# define R300_SWIZZLE_SELECT_W 3 -# define R300_SWIZZLE_SELECT_FP_ZERO 4 -# define R300_SWIZZLE_SELECT_FP_ONE 5 -/* alternate forms for r300_emit.c */ -# define R300_INPUT_ROUTE_SELECT_X 0 -# define R300_INPUT_ROUTE_SELECT_Y 1 -# define R300_INPUT_ROUTE_SELECT_Z 2 -# define R300_INPUT_ROUTE_SELECT_W 3 -# define R300_INPUT_ROUTE_SELECT_ZERO 4 -# define R300_INPUT_ROUTE_SELECT_ONE 5 - -# define R300_WRITE_ENA_SHIFT 12 -# define R300_WRITE_ENA_X 1 -# define R300_WRITE_ENA_Y 2 -# define R300_WRITE_ENA_Z 4 -# define R300_WRITE_ENA_W 8 -# define R300_SWIZZLE1_SHIFT 16 -#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 -#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8 -#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec -#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0 -#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4 -#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8 -#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc - -/* END: Vertex data assembly */ - -/* gap */ - -/* BEGIN: Upload vertex program and data */ - -/* - * The programmable vertex shader unit has a memory bank of unknown size - * that can be written to in 16 byte units by writing the address into - * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). - * - * Pointers into the memory bank are always in multiples of 16 bytes. - * - * The memory bank is divided into areas with fixed meaning. - * - * Starting at address UPLOAD_PROGRAM: Vertex program instructions. - * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), - * whereas the difference between known addresses suggests size 512. - * - * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. - * Native reported limits and the VPI layout suggest size 256, whereas - * difference between known addresses suggests size 512. - * - * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the - * floating point pointsize. The exact purpose of this state is uncertain, - * as there is also the R300_RE_POINTSIZE register. - * - * Multiple vertex programs and parameter sets can be loaded at once, - * which could explain the size discrepancy. - */ -#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 -# define R300_PVS_CODE_START 0 -# define R300_MAX_PVS_CODE_LINES 256 -# define R500_MAX_PVS_CODE_LINES 1024 -# define R300_PVS_CONST_START 512 -# define R500_PVS_CONST_START 1024 -# define R300_MAX_PVS_CONST_VECS 256 -# define R500_MAX_PVS_CONST_VECS 1024 -# define R300_PVS_UCP_START 1024 -# define R500_PVS_UCP_START 1536 -# define R300_POINT_VPORT_SCALE_OFFSET 1030 -# define R500_POINT_VPORT_SCALE_OFFSET 1542 -# define R300_POINT_GEN_TEX_OFFSET 1031 -# define R500_POINT_GEN_TEX_OFFSET 1543 - -/* - * These are obsolete defines form r300_context.h, but they might give some - * clues when investigating the addresses further... - */ -#if 0 -#define VSF_DEST_PROGRAM 0x0 -#define VSF_DEST_MATRIX0 0x200 -#define VSF_DEST_MATRIX1 0x204 -#define VSF_DEST_MATRIX2 0x208 -#define VSF_DEST_VECTOR0 0x20c -#define VSF_DEST_VECTOR1 0x20d -#define VSF_DEST_UNKNOWN1 0x400 -#define VSF_DEST_UNKNOWN2 0x406 -#endif - -/* gap */ - -#define R300_VAP_PVS_UPLOAD_DATA 0x2208 - -/* END: Upload vertex program and data */ - -/* gap */ - -/* I do not know the purpose of this register. However, I do know that - * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL - * for normal rendering. - * - * 2007-11-05: This register is the user clip plane control register, but there - * also seems to be a rendering mode control; the NORMAL/CLEAR defines. - * - * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view - */ -#define R300_VAP_CLIP_CNTL 0x221C -# define R300_VAP_UCP_ENABLE_0 (1 << 0) -# define R300_VAP_UCP_ENABLE_1 (1 << 1) -# define R300_VAP_UCP_ENABLE_2 (1 << 2) -# define R300_VAP_UCP_ENABLE_3 (1 << 3) -# define R300_VAP_UCP_ENABLE_4 (1 << 4) -# define R300_VAP_UCP_ENABLE_5 (1 << 5) -# define R300_PS_UCP_MODE_DIST_COP (0 << 14) -# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14) -# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14) -# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14) -# define R300_CLIP_DISABLE (1 << 16) -# define R300_UCP_CULL_ONLY_ENABLE (1 << 17) -# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) -# define R500_COLOR2_IS_TEXTURE (1 << 20) -# define R500_COLOR3_IS_TEXTURE (1 << 21) - -/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first - * plane is per-pixel and the second plane is per-vertex. - * - * This was determined by experimentation alone but I believe it is correct. - * - * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. - */ -#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 -#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 -#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 -#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c - -#define R300_VAP_PVS_FLOW_CNTL_ADDRS_0 0x2230 -#define R300_PVS_FC_ACT_ADRS(x) ((x) << 0) -#define R300_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 8) -#define R300_PVS_FC_LAST_INST(x) ((x) << 16) -#define R300_PVS_FC_RTN_INST(x) ((x) << 24) - -/* gap */ - -/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between - * rendering commands and overwriting vertex program parameters. - * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and - * avoids bugs caused by still running shaders reading bad data from memory. - */ -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 - -/* This register is used to define the number of core clocks to wait for a - * vertex to be received by the VAP input controller (while the primitive - * path is backed up) before forcing any accumulated vertices to be submitted - * to the vertex processing path. - */ -#define VAP_PVS_VTX_TIMEOUT_REG 0x2288 -# define R300_2288_R300 0x00750000 /* -- nh */ -# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ - -#define R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 0x2290 -#define R300_PVS_FC_LOOP_INIT_VAL(x) ((x) << 0) -#define R300_PVS_FC_LOOP_STEP_VAL(x) ((x) << 8) - -/* gap */ - -/* Addresses are relative to the vertex program instruction area of the - * memory bank. PROGRAM_END points to the last instruction of the active - * program - * - * The meaning of the two UNKNOWN fields is obviously not known. However, - * experiments so far have shown that both *must* point to an instruction - * inside the vertex program, otherwise the GPU locks up. - * - * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and - * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to - * position takes place. - * - * Most likely this is used to ignore rest of the program in cases - * where group of verts arent visible. For some reason this "section" - * is sometimes accepted other instruction that have no relationship with - * position calculations. - */ -#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 -# define R300_PVS_FIRST_INST_SHIFT 0 -# define R300_PVS_XYZW_VALID_INST_SHIFT 10 -# define R300_PVS_LAST_INST_SHIFT 20 -/* Addresses are relative to the vertex program parameters area. */ -#define R300_VAP_PVS_CONST_CNTL 0x22D4 -# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0 -# define R300_PVS_MAX_CONST_ADDR_SHIFT 16 -#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 -# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 -#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC -#define R300_VAP_PVS_FC_OPC_JUMP(x) (1 << (2 * (x))) -#define R300_VAP_PVS_FC_OPC_LOOP(x) (2 << (2 * (x))) -#define R300_VAP_PVS_FC_OPC_JSR(x) (3 << (2 * (x))) - -/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for - * immediate vertices - */ -#define R300_VAP_VTX_COLOR_R 0x2464 -#define R300_VAP_VTX_COLOR_G 0x2468 -#define R300_VAP_VTX_COLOR_B 0x246C -#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ -#define R300_VAP_VTX_POS_0_Y_1 0x2494 -#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ -#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ -#define R300_VAP_VTX_POS_0_Y_2 0x24A4 -#define R300_VAP_VTX_POS_0_Z_2 0x24A8 -/* write 0 to indicate end of packet? */ -#define R300_VAP_VTX_END_OF_PKT 0x24AC - -#define R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0 0x2500 -#define R500_PVS_FC_ACT_ADRS(x) ((x) << 0) -#define R500_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 16) - -#define R500_VAP_PVS_FLOW_CNTL_ADDRS_UW_0 0x2504 -#define R500_PVS_FC_LAST_INST(x) ((x) << 0) -#define R500_PVS_FC_RTN_INST(x) ((x) << 16) - -/* gap */ - -/* These are values from r300_reg/r300_reg.h - they are known to be correct - * and are here so we can use one register file instead of several - * - Vladimir - */ -#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 -# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) -# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) - -#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 - /* each of the following is 3 bits wide, specifies number - of components */ -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 - -/* UNK30 seems to enables point to quad transformation on textures - * (or something closely related to that). - * This bit is rather fatal at the time being due to lackings at pixel - * shader side - * Specifies top of Raster pipe specific enable controls. - */ -#define R300_GB_ENABLE 0x4008 -# define R300_GB_POINT_STUFF_DISABLE (0 << 0) -# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */ -# define R300_GB_LINE_STUFF_DISABLE (0 << 1) -# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */ -# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2) -# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */ -# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4) -# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */ -# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */ - - /* each of the following is 2 bits wide */ -#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */ -#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */ -#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */ -# define R300_GB_TEX0_SOURCE_SHIFT 16 -# define R300_GB_TEX1_SOURCE_SHIFT 18 -# define R300_GB_TEX2_SOURCE_SHIFT 20 -# define R300_GB_TEX3_SOURCE_SHIFT 22 -# define R300_GB_TEX4_SOURCE_SHIFT 24 -# define R300_GB_TEX5_SOURCE_SHIFT 26 -# define R300_GB_TEX6_SOURCE_SHIFT 28 -# define R300_GB_TEX7_SOURCE_SHIFT 30 - -/* MSPOS - positions for multisample antialiasing (?) */ -#define R300_GB_MSPOS0 0x4010 - /* shifts - each of the fields is 4 bits */ -# define R300_GB_MSPOS0__MS_X0_SHIFT 0 -# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 -# define R300_GB_MSPOS0__MS_X1_SHIFT 8 -# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 -# define R300_GB_MSPOS0__MS_X2_SHIFT 16 -# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 -# define R300_GB_MSPOS0__MSBD0_Y 24 -# define R300_GB_MSPOS0__MSBD0_X 28 - -#define R300_GB_MSPOS1 0x4014 -# define R300_GB_MSPOS1__MS_X3_SHIFT 0 -# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 -# define R300_GB_MSPOS1__MS_X4_SHIFT 8 -# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 -# define R300_GB_MSPOS1__MS_X5_SHIFT 16 -# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 -# define R300_GB_MSPOS1__MSBD1 24 - -/* Specifies the graphics pipeline configuration for rasterization. */ -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_GB_TILE_DISABLE (0 << 0) -# define R300_GB_TILE_ENABLE (1 << 0) -# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */ -# define R300_GB_TILE_SIZE_8 (0 << 4) -# define R300_GB_TILE_SIZE_16 (1 << 4) -# define R300_GB_TILE_SIZE_32 (2 << 4) -# define R300_GB_SUPER_SIZE_1 (0 << 6) -# define R300_GB_SUPER_SIZE_2 (1 << 6) -# define R300_GB_SUPER_SIZE_4 (2 << 6) -# define R300_GB_SUPER_SIZE_8 (3 << 6) -# define R300_GB_SUPER_SIZE_16 (4 << 6) -# define R300_GB_SUPER_SIZE_32 (5 << 6) -# define R300_GB_SUPER_SIZE_64 (6 << 6) -# define R300_GB_SUPER_SIZE_128 (7 << 6) -# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ -# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ -# define R300_GB_SUPER_TILE_A (0 << 15) -# define R300_GB_SUPER_TILE_B (1 << 15) -# define R300_GB_SUBPIXEL_1_12 (0 << 16) -# define R300_GB_SUBPIXEL_1_16 (1 << 16) -# define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17) -# define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17) -# define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17) -# define GB_TILE_CONFIG_QUADS_PER_RAS_32 (3 << 17) -# define GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19) -# define GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19) -# define GB_TILE_CONFIG_ALT_SCAN_EN_LR (0 << 20) -# define GB_TILE_CONFIG_ALT_SCAN_EN_LRL (1 << 20) -# define GB_TILE_CONFIG_ALT_OFFSET (0 << 21) -# define GB_TILE_CONFIG_SUBPRECISION (0 << 22) -# define GB_TILE_CONFIG_ALT_TILING_DEF (0 << 23) -# define GB_TILE_CONFIG_ALT_TILING_3_2 (1 << 23) -# define GB_TILE_CONFIG_Z_EXTENDED_24_1 (0 << 24) -# define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24) - -/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */ -#define R300_GB_FIFO_SIZE 0x4024 - /* each of the following is 2 bits wide */ -#define R300_GB_FIFO_SIZE_32 0 -#define R300_GB_FIFO_SIZE_64 1 -#define R300_GB_FIFO_SIZE_128 2 -#define R300_GB_FIFO_SIZE_256 3 -# define R300_SC_IFIFO_SIZE_SHIFT 0 -# define R300_SC_TZFIFO_SIZE_SHIFT 2 -# define R300_SC_BFIFO_SIZE_SHIFT 4 - -# define R300_US_OFIFO_SIZE_SHIFT 12 -# define R300_US_WFIFO_SIZE_SHIFT 14 - /* the following use the same constants as above, but meaning is - is times 2 (i.e. instead of 32 words it means 64 */ -# define R300_RS_TFIFO_SIZE_SHIFT 6 -# define R300_RS_CFIFO_SIZE_SHIFT 8 -# define R300_US_RAM_SIZE_SHIFT 10 - /* watermarks, 3 bits wide */ -# define R300_RS_HIGHWATER_COL_SHIFT 16 -# define R300_RS_HIGHWATER_TEX_SHIFT 19 -# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ -# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 - -#define GB_Z_PEQ_CONFIG 0x4028 -# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0) -# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0) - -/* Specifies various polygon specific selects (fog, depth, perspective). */ -#define R300_GB_SELECT 0x401c -# define R300_GB_FOG_SELECT_C0A (0 << 0) -# define R300_GB_FOG_SELECT_C1A (1 << 0) -# define R300_GB_FOG_SELECT_C2A (2 << 0) -# define R300_GB_FOG_SELECT_C3A (3 << 0) -# define R300_GB_FOG_SELECT_1_1_W (4 << 0) -# define R300_GB_FOG_SELECT_Z (5 << 0) -# define R300_GB_DEPTH_SELECT_Z (0 << 3) -# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3) -# define R300_GB_W_SELECT_1_W (0 << 4) -# define R300_GB_W_SELECT_1 (1 << 4) -# define R300_GB_FOG_STUFF_DISABLE (0 << 5) -# define R300_GB_FOG_STUFF_ENABLE (1 << 5) -# define R300_GB_FOG_STUFF_TEX_SHIFT 6 -# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0 -# define R300_GB_FOG_STUFF_COMP_SHIFT 10 -# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00 - -/* Specifies the graphics pipeline configuration for antialiasing. */ -#define GB_AA_CONFIG 0x4020 -# define GB_AA_CONFIG_AA_DISABLE (0 << 0) -# define GB_AA_CONFIG_AA_ENABLE (1 << 0) -# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1) -# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3 (1 << 1) -# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4 (2 << 1) -# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6 (3 << 1) - -/* Selects which of 4 pipes are active. */ -#define GB_PIPE_SELECT 0x402c -# define GB_PIPE_SELECT_PIPE0_ID_SHIFT 0 -# define GB_PIPE_SELECT_PIPE1_ID_SHIFT 2 -# define GB_PIPE_SELECT_PIPE2_ID_SHIFT 4 -# define GB_PIPE_SELECT_PIPE3_ID_SHIFT 6 -# define GB_PIPE_SELECT_PIPE_MASK_SHIFT 8 -# define GB_PIPE_SELECT_MAX_PIPE 12 -# define GB_PIPE_SELECT_BAD_PIPES 14 -# define GB_PIPE_SELECT_CONFIG_PIPES 18 - - -/* Specifies the sizes of the various FIFO`s in the sc/rs. */ -#define GB_FIFO_SIZE1 0x4070 -/* High water mark for SC input fifo */ -# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0 -# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK 0x0000003f -/* High water mark for SC input fifo (B) */ -# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6 -# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK 0x00000fc0 -/* High water mark for RS colors' fifo */ -# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT 12 -# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK 0x0003f000 -/* High water mark for RS textures' fifo */ -# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18 -# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000 - -/* This table specifies the source location and format for up to 16 texture - * addresses (i[0]:i[15]) and four colors (c[0]:c[3]) - */ -#define R500_RS_IP_0 0x4074 -#define R500_RS_IP_1 0x4078 -#define R500_RS_IP_2 0x407C -#define R500_RS_IP_3 0x4080 -#define R500_RS_IP_4 0x4084 -#define R500_RS_IP_5 0x4088 -#define R500_RS_IP_6 0x408C -#define R500_RS_IP_7 0x4090 -#define R500_RS_IP_8 0x4094 -#define R500_RS_IP_9 0x4098 -#define R500_RS_IP_10 0x409C -#define R500_RS_IP_11 0x40A0 -#define R500_RS_IP_12 0x40A4 -#define R500_RS_IP_13 0x40A8 -#define R500_RS_IP_14 0x40AC -#define R500_RS_IP_15 0x40B0 -#define R500_RS_IP_PTR_K0 62 -#define R500_RS_IP_PTR_K1 63 -#define R500_RS_IP_TEX_PTR_S_SHIFT 0 -#define R500_RS_IP_TEX_PTR_T_SHIFT 6 -#define R500_RS_IP_TEX_PTR_R_SHIFT 12 -#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 -#define R500_RS_IP_COL_PTR_SHIFT 24 -#define R500_RS_IP_COL_FMT_SHIFT 27 -# define R500_RS_COL_PTR(x) ((x) << 24) -# define R500_RS_COL_FMT(x) ((x) << 27) -/* gap */ -#define R500_RS_IP_OFFSET_DIS (0 << 31) -#define R500_RS_IP_OFFSET_EN (1 << 31) - -/* gap */ - -/* Zero to flush caches. */ -#define R300_TX_INVALTAGS 0x4100 -#define R300_TX_FLUSH 0x0 - -/* The upper enable bits are guessed, based on fglrx reported limits. */ -#define R300_TX_ENABLE 0x4104 -# define R300_TX_ENABLE_0 (1 << 0) -# define R300_TX_ENABLE_1 (1 << 1) -# define R300_TX_ENABLE_2 (1 << 2) -# define R300_TX_ENABLE_3 (1 << 3) -# define R300_TX_ENABLE_4 (1 << 4) -# define R300_TX_ENABLE_5 (1 << 5) -# define R300_TX_ENABLE_6 (1 << 6) -# define R300_TX_ENABLE_7 (1 << 7) -# define R300_TX_ENABLE_8 (1 << 8) -# define R300_TX_ENABLE_9 (1 << 9) -# define R300_TX_ENABLE_10 (1 << 10) -# define R300_TX_ENABLE_11 (1 << 11) -# define R300_TX_ENABLE_12 (1 << 12) -# define R300_TX_ENABLE_13 (1 << 13) -# define R300_TX_ENABLE_14 (1 << 14) -# define R300_TX_ENABLE_15 (1 << 15) - -#define R500_TX_FILTER_4 0x4110 -# define R500_TX_WEIGHT_1_SHIFT (0) -# define R500_TX_WEIGHT_0_SHIFT (11) -# define R500_TX_WEIGHT_PAIR (1<<22) -# define R500_TX_PHASE_SHIFT (23) -# define R500_TX_DIRECTION_HORIZONTAL (0<<27) -# define R500_TX_DIRECTION_VERITCAL (1<<27) - -/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ -#define R300_GA_POINT_S0 0x4200 - -/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ -#define R300_GA_POINT_T0 0x4204 - -/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ -#define R300_GA_POINT_S1 0x4208 - -/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ -#define R300_GA_POINT_T1 0x420c - -/* Specifies amount to shift integer position of vertex (screen space) before - * converting to float for triangle stipple. - */ -#define R300_GA_TRIANGLE_STIPPLE 0x4214 -# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0 -# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f -# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16 -# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000 - -/* The pointsize is given in multiples of 6. The pointsize can be enormous: - * Clear() renders a single point that fills the entire framebuffer. - * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in - * 8b precision). - */ -#define R300_GA_POINT_SIZE 0x421C -# define R300_POINTSIZE_Y_SHIFT 0 -# define R300_POINTSIZE_Y_MASK 0x0000ffff -# define R300_POINTSIZE_X_SHIFT 16 -# define R300_POINTSIZE_X_MASK 0xffff0000 -# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) - -/* Blue fill color */ -#define R500_GA_FILL_R 0x4220 - -/* Blue fill color */ -#define R500_GA_FILL_G 0x4224 - -/* Blue fill color */ -#define R500_GA_FILL_B 0x4228 - -/* Alpha fill color */ -#define R500_GA_FILL_A 0x422c - - -/* Specifies maximum and minimum point & sprite sizes for per vertex size - * specification. The lower part (15:0) is MIN and (31:16) is max. - */ -#define R300_GA_POINT_MINMAX 0x4230 -# define R300_GA_POINT_MINMAX_MIN_SHIFT 0 -# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0) -# define R300_GA_POINT_MINMAX_MAX_SHIFT 16 -# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16) - -/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b - * subprecision); (16.0) fixed format. - * - * The line width is given in multiples of 6. - * In default mode lines are classified as vertical lines. - * HO: horizontal - * VE: vertical or horizontal - * HO & VE: no classification - */ -#define R300_GA_LINE_CNTL 0x4234 -# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0 -# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff -# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16) -# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16) -# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ -# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ -# define R500_GA_LINE_CNTL_SORT_NO (0 << 18) -# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) -/** TODO: looks wrong */ -# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6) -/** TODO: looks wrong */ -# define R300_LINE_CNT_HO (1 << 16) -/** TODO: looks wrong */ -# define R300_LINE_CNT_VE (1 << 17) - -/* Line Stipple configuration information. */ -#define R300_GA_LINE_STIPPLE_CONFIG 0x4238 -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 -# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc - -/* Used to load US instructions and constants */ -#define R500_GA_US_VECTOR_INDEX 0x4250 -# define R500_GA_US_VECTOR_INDEX_SHIFT 0 -# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff -# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16) -# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16) -# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17) -# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17) - -/* Data register for loading US instructions and constants */ -#define R500_GA_US_VECTOR_DATA 0x4254 - -/* Specifies color properties and mappings of textures. */ -#define R500_GA_COLOR_CONTROL_PS3 0x4258 -# define R500_TEX0_SHADING_PS3_SOLID (0 << 0) -# define R500_TEX0_SHADING_PS3_FLAT (1 << 0) -# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0) -# define R500_TEX1_SHADING_PS3_SOLID (0 << 2) -# define R500_TEX1_SHADING_PS3_FLAT (1 << 2) -# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2) -# define R500_TEX2_SHADING_PS3_SOLID (0 << 4) -# define R500_TEX2_SHADING_PS3_FLAT (1 << 4) -# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4) -# define R500_TEX3_SHADING_PS3_SOLID (0 << 6) -# define R500_TEX3_SHADING_PS3_FLAT (1 << 6) -# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6) -# define R500_TEX4_SHADING_PS3_SOLID (0 << 8) -# define R500_TEX4_SHADING_PS3_FLAT (1 << 8) -# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8) -# define R500_TEX5_SHADING_PS3_SOLID (0 << 10) -# define R500_TEX5_SHADING_PS3_FLAT (1 << 10) -# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10) -# define R500_TEX6_SHADING_PS3_SOLID (0 << 12) -# define R500_TEX6_SHADING_PS3_FLAT (1 << 12) -# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12) -# define R500_TEX7_SHADING_PS3_SOLID (0 << 14) -# define R500_TEX7_SHADING_PS3_FLAT (1 << 14) -# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14) -# define R500_TEX8_SHADING_PS3_SOLID (0 << 16) -# define R500_TEX8_SHADING_PS3_FLAT (1 << 16) -# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16) -# define R500_TEX9_SHADING_PS3_SOLID (0 << 18) -# define R500_TEX9_SHADING_PS3_FLAT (1 << 18) -# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18) -# define R500_TEX10_SHADING_PS3_SOLID (0 << 20) -# define R500_TEX10_SHADING_PS3_FLAT (1 << 20) -# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20) -# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22) -# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26) - -/* Returns idle status of various G3D block, captured when GA_IDLE written or - * when hard or soft reset asserted. - */ -#define R500_GA_IDLE 0x425c -# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0) -# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1) -# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2) -# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3) -# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4) -# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5) -# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6) -# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7) -# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8) -# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9) -# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10) -# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11) -# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12) -# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13) -# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14) -# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15) -# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16) -# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17) -# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18) -# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19) -# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20) -# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21) -# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22) -# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23) -# define R500_GA_IDLE_SU_IDLE (0 << 24) -# define R500_GA_IDLE_GA_IDLE (0 << 25) -# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26) - -/* Current value of stipple accumulator. */ -#define R300_GA_LINE_STIPPLE_VALUE 0x4260 - -/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */ -#define R300_GA_LINE_S0 0x4264 -/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */ -#define R300_GA_LINE_S1 0x4268 - -/* GA Input fifo high water marks */ -#define R500_GA_FIFO_CNTL 0x4270 -# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007 -# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0 -# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038 -# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3 -# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0 -# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6 - -/* GA enhance/tweaks */ -#define R300_GA_ENHANCE 0x4274 -# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) -# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ -# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) -# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ -# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */ -# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */ -# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3) -# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */ - -#define R300_GA_COLOR_CONTROL 0x4278 -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0) -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16) - -/** TODO: might be candidate for removal */ -# define R300_RE_SHADE_MODEL_SMOOTH ( \ - R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD) -/** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */ -# define R300_RE_SHADE_MODEL_FLAT ( \ - R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \ - R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \ - R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD) - -/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */ -#define R300_GA_SOLID_RG 0x427c -# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0 -# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff -# define GA_SOLID_RG_COLOR_RED_SHIFT 16 -# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000 -/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */ -#define R300_GA_SOLID_BA 0x4280 -# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0 -# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff -# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16 -# define GA_SOLID_BA_COLOR_BLUE_MASK 0xffff0000 - -/* Polygon Mode - * Dangerous - */ -#define R300_GA_POLY_MODE 0x4288 -# define R300_GA_POLY_MODE_DISABLE (0 << 0) -# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */ -/* reserved */ -# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4) -# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4) -# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4) -/* reserved */ -# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7) -# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7) -# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7) -/* reserved */ - -/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */ -#define R300_GA_ROUND_MODE 0x428c -# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0) -# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0) -# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2) -# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2) -# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4) -# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) -# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) -# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) -# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6 -# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0 - -/* Specifies x & y offsets for vertex data after conversion to FP. - * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b - * subprecision). - */ -#define R300_GA_OFFSET 0x4290 -# define R300_GA_OFFSET_X_OFFSET_SHIFT 0 -# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff -# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16 -# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000 - -/* Specifies the scale to apply to fog. */ -#define R300_GA_FOG_SCALE 0x4294 -/* Specifies the offset to apply to fog. */ -#define R300_GA_FOG_OFFSET 0x4298 -/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */ -#define R300_GA_SOFT_RESET 0x429c - -/* Not sure why there are duplicate of factor and constant values. - * My best guess so far is that there are seperate zbiases for test and write. - * Ordering might be wrong. - * Some of the tests indicate that fgl has a fallback implementation of zbias - * via pixel shaders. - */ -#define R300_SU_TEX_WRAP 0x42A0 -#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4 -#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8 -#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC -#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0 - -/* This register needs to be set to (1<<1) for RV350 to correctly - * perform depth test (see --vb-triangles in r300_demo) - * Don't know about other chips. - Vladimir - * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. - * My guess is that there are two bits for each zbias primitive - * (FILL, LINE, POINT). - * One to enable depth test and one for depth write. - * Yet this doesnt explain why depth writes work ... - */ -#define R300_SU_POLY_OFFSET_ENABLE 0x42B4 -# define R300_FRONT_ENABLE (1 << 0) -# define R300_BACK_ENABLE (1 << 1) -# define R300_PARA_ENABLE (1 << 2) - -#define R300_SU_CULL_MODE 0x42B8 -# define R300_CULL_FRONT (1 << 0) -# define R300_CULL_BACK (1 << 1) -# define R300_FRONT_FACE_CCW (0 << 2) -# define R300_FRONT_FACE_CW (1 << 2) - -/* SU Depth Scale value */ -#define R300_SU_DEPTH_SCALE 0x42c0 -/* SU Depth Offset value */ -#define R300_SU_DEPTH_OFFSET 0x42c4 - -#define R300_SU_REG_DEST 0x42c8 -# define R300_RASTER_PIPE_SELECT_0 (1 << 0) -# define R300_RASTER_PIPE_SELECT_1 (1 << 1) -# define R300_RASTER_PIPE_SELECT_2 (1 << 2) -# define R300_RASTER_PIPE_SELECT_3 (1 << 3) -# define R300_RASTER_PIPE_SELECT_ALL 0xf - - -/* BEGIN: Rasterization / Interpolators - many guesses */ - -/* - * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends - * on the vertex program, *not* the fragment program) - */ -#define R300_RS_COUNT 0x4300 -# define R300_IT_COUNT_SHIFT 0 -# define R300_IT_COUNT_MASK 0x0000007f -# define R300_IC_COUNT_SHIFT 7 -# define R300_IC_COUNT_MASK 0x00000780 -# define R300_W_ADDR_SHIFT 12 -# define R300_W_ADDR_MASK 0x0003f000 -# define R300_HIRES_DIS (0 << 18) -# define R300_HIRES_EN (1 << 18) - -#define R300_RS_INST_COUNT 0x4304 -# define R300_RS_INST_COUNT_SHIFT 0 -# define R300_RS_INST_COUNT_MASK 0x0000000f -# define R300_RS_TX_OFFSET_SHIFT 5 -# define R300_RS_TX_OFFSET_MASK 0x000000e0 - -/* gap */ - -/* Only used for texture coordinates. - * Use the source field to route texture coordinate input from the - * vertex program to the desired interpolator. Note that the source - * field is relative to the outputs the vertex program *actually* - * writes. If a vertex program only writes texcoord[1], this will - * be source index 0. - * Set INTERP_USED on all interpolators that produce data used by - * the fragment program. INTERP_USED looks like a swizzling mask, - * but I haven't seen it used that way. - * - * Note: The _UNKNOWN constants are always set in their respective - * register. I don't know if this is necessary. - */ -#define R300_RS_IP_0 0x4310 -#define R300_RS_IP_1 0x4314 -#define R300_RS_IP_2 0x4318 -#define R300_RS_IP_3 0x431C -# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ -# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ -# define R300_RS_TEX_PTR(x) ((x) << 0) -# define R300_RS_COL_PTR(x) ((x) << 6) -# define R300_RS_COL_FMT(x) ((x) << 9) -# define R300_RS_COL_FMT_RGBA 0 -# define R300_RS_COL_FMT_RGB0 1 -# define R300_RS_COL_FMT_RGB1 2 -# define R300_RS_COL_FMT_000A 4 -# define R300_RS_COL_FMT_0000 5 -# define R300_RS_COL_FMT_0001 6 -# define R300_RS_COL_FMT_111A 8 -# define R300_RS_COL_FMT_1110 9 -# define R300_RS_COL_FMT_1111 10 -# define R300_RS_SEL_S(x) ((x) << 13) -# define R300_RS_SEL_T(x) ((x) << 16) -# define R300_RS_SEL_R(x) ((x) << 19) -# define R300_RS_SEL_Q(x) ((x) << 22) -# define R300_RS_SEL_C0 0 -# define R300_RS_SEL_C1 1 -# define R300_RS_SEL_C2 2 -# define R300_RS_SEL_C3 3 -# define R300_RS_SEL_K0 4 -# define R300_RS_SEL_K1 5 - - -/* */ -#define R500_RS_INST_0 0x4320 -#define R500_RS_INST_1 0x4324 -#define R500_RS_INST_2 0x4328 -#define R500_RS_INST_3 0x432c -#define R500_RS_INST_4 0x4330 -#define R500_RS_INST_5 0x4334 -#define R500_RS_INST_6 0x4338 -#define R500_RS_INST_7 0x433c -#define R500_RS_INST_8 0x4340 -#define R500_RS_INST_9 0x4344 -#define R500_RS_INST_10 0x4348 -#define R500_RS_INST_11 0x434c -#define R500_RS_INST_12 0x4350 -#define R500_RS_INST_13 0x4354 -#define R500_RS_INST_14 0x4358 -#define R500_RS_INST_15 0x435c -#define R500_RS_INST_TEX_ID_SHIFT 0 -#define R500_RS_INST_TEX_CN_WRITE (1 << 4) -#define R500_RS_INST_TEX_ADDR_SHIFT 5 -#define R500_RS_INST_COL_ID_SHIFT 12 -#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) -#define R500_RS_INST_COL_CN_WRITE (1 << 16) -#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) -#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) -#define R500_RS_INST_COL_ADDR_SHIFT 18 -#define R500_RS_INST_TEX_ADJ (1 << 25) -#define R500_RS_INST_W_CN (1 << 26) -#define R500_RS_INST_TEX_ID(x) ((x) << R500_RS_INST_TEX_ID_SHIFT) -#define R500_RS_INST_TEX_ADDR(x) ((x) << R500_RS_INST_TEX_ADDR_SHIFT) -#define R500_RS_INST_COL_ID(x) ((x) << R500_RS_INST_COL_ID_SHIFT) -#define R500_RS_INST_COL_ADDR(x) ((x) << R500_RS_INST_COL_ADDR_SHIFT) - -/* These DWORDs control how vertex data is routed into fragment program - * registers, after interpolators. - */ -#define R300_RS_INST_0 0x4330 -#define R300_RS_INST_1 0x4334 -#define R300_RS_INST_2 0x4338 -#define R300_RS_INST_3 0x433C /* GUESS */ -#define R300_RS_INST_4 0x4340 /* GUESS */ -#define R300_RS_INST_5 0x4344 /* GUESS */ -#define R300_RS_INST_6 0x4348 /* GUESS */ -#define R300_RS_INST_7 0x434C /* GUESS */ -# define R300_RS_INST_TEX_ID(x) ((x) << 0) -# define R300_RS_INST_TEX_CN_WRITE (1 << 3) -# define R300_RS_INST_TEX_ADDR_SHIFT 6 -# define R300_RS_INST_TEX_ADDR(x) ((x) << R300_RS_INST_TEX_ADDR_SHIFT) -# define R300_RS_INST_COL_ID(x) ((x) << 11) -# define R300_RS_INST_COL_CN_WRITE (1 << 14) -# define R300_RS_INST_COL_ADDR_SHIFT 17 -# define R300_RS_INST_COL_ADDR(x) ((x) << R300_RS_INST_COL_ADDR_SHIFT) -# define R300_RS_INST_TEX_ADJ (1 << 22) -# define R300_RS_COL_BIAS_UNUSED_SHIFT 23 - -/* END: Rasterization / Interpolators - many guesses */ - -/* Hierarchical Z Enable */ -#define R300_SC_HYPERZ 0x43a4 -# define R300_SC_HYPERZ_DISABLE (0 << 0) -# define R300_SC_HYPERZ_ENABLE (1 << 0) -# define R300_SC_HYPERZ_MIN (0 << 1) -# define R300_SC_HYPERZ_MAX (1 << 1) -# define R300_SC_HYPERZ_ADJ_256 (0 << 2) -# define R300_SC_HYPERZ_ADJ_128 (1 << 2) -# define R300_SC_HYPERZ_ADJ_64 (2 << 2) -# define R300_SC_HYPERZ_ADJ_32 (3 << 2) -# define R300_SC_HYPERZ_ADJ_16 (4 << 2) -# define R300_SC_HYPERZ_ADJ_8 (5 << 2) -# define R300_SC_HYPERZ_ADJ_4 (6 << 2) -# define R300_SC_HYPERZ_ADJ_2 (7 << 2) -# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) -# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) -# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) -# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) - -#define R300_SC_EDGERULE 0x43a8 - -/* BEGIN: Scissors and cliprects */ - -/* There are four clipping rectangles. Their corner coordinates are inclusive. - * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending - * on whether the pixel is inside cliprects 0-3, respectively. For example, - * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned - * the number 3 (binary 0011). - * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, - * the pixel is rasterized. - * - * In addition to this, there is a scissors rectangle. Only pixels inside the - * scissors rectangle are drawn. (coordinates are inclusive) - * - * For some reason, the top-left corner of the framebuffer is at (1440, 1440) - * for the purpose of clipping and scissors. - */ -#define R300_SC_CLIPRECT_TL_0 0x43B0 -#define R300_SC_CLIPRECT_BR_0 0x43B4 -#define R300_SC_CLIPRECT_TL_1 0x43B8 -#define R300_SC_CLIPRECT_BR_1 0x43BC -#define R300_SC_CLIPRECT_TL_2 0x43C0 -#define R300_SC_CLIPRECT_BR_2 0x43C4 -#define R300_SC_CLIPRECT_TL_3 0x43C8 -#define R300_SC_CLIPRECT_BR_3 0x43CC -# define R300_CLIPRECT_OFFSET 1440 -# define R300_CLIPRECT_MASK 0x1FFF -# define R300_CLIPRECT_X_SHIFT 0 -# define R300_CLIPRECT_X_MASK (0x1FFF << 0) -# define R300_CLIPRECT_Y_SHIFT 13 -# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) -#define R300_SC_CLIP_RULE 0x43D0 -# define R300_CLIP_OUT (1 << 0) -# define R300_CLIP_0 (1 << 1) -# define R300_CLIP_1 (1 << 2) -# define R300_CLIP_10 (1 << 3) -# define R300_CLIP_2 (1 << 4) -# define R300_CLIP_20 (1 << 5) -# define R300_CLIP_21 (1 << 6) -# define R300_CLIP_210 (1 << 7) -# define R300_CLIP_3 (1 << 8) -# define R300_CLIP_30 (1 << 9) -# define R300_CLIP_31 (1 << 10) -# define R300_CLIP_310 (1 << 11) -# define R300_CLIP_32 (1 << 12) -# define R300_CLIP_320 (1 << 13) -# define R300_CLIP_321 (1 << 14) -# define R300_CLIP_3210 (1 << 15) - -/* gap */ - -#define R300_SC_SCISSORS_TL 0x43E0 -#define R300_SC_SCISSORS_BR 0x43E4 -# define R300_SCISSORS_OFFSET 1440 -# define R300_SCISSORS_X_SHIFT 0 -# define R300_SCISSORS_X_MASK (0x1FFF << 0) -# define R300_SCISSORS_Y_SHIFT 13 -# define R300_SCISSORS_Y_MASK (0x1FFF << 13) - -/* Screen door sample mask */ -#define R300_SC_SCREENDOOR 0x43e8 - -/* END: Scissors and cliprects */ - -/* BEGIN: Texture specification */ - -/* - * The texture specification dwords are grouped by meaning and not by texture - * unit. This means that e.g. the offset for texture image unit N is found in - * register TX_OFFSET_0 + (4*N) - */ -#define R300_TX_FILTER0_0 0x4400 -#define R300_TX_FILTER0_1 0x4404 -#define R300_TX_FILTER0_2 0x4408 -#define R300_TX_FILTER0_3 0x440c -#define R300_TX_FILTER0_4 0x4410 -#define R300_TX_FILTER0_5 0x4414 -#define R300_TX_FILTER0_6 0x4418 -#define R300_TX_FILTER0_7 0x441c -#define R300_TX_FILTER0_8 0x4420 -#define R300_TX_FILTER0_9 0x4424 -#define R300_TX_FILTER0_10 0x4428 -#define R300_TX_FILTER0_11 0x442c -#define R300_TX_FILTER0_12 0x4430 -#define R300_TX_FILTER0_13 0x4434 -#define R300_TX_FILTER0_14 0x4438 -#define R300_TX_FILTER0_15 0x443c -# define R300_TX_REPEAT 0 -# define R300_TX_MIRRORED 1 -# define R300_TX_CLAMP_TO_EDGE 2 -# define R300_TX_MIRROR_ONCE_TO_EDGE 3 -# define R300_TX_CLAMP 4 -# define R300_TX_MIRROR_ONCE 5 -# define R300_TX_CLAMP_TO_BORDER 6 -# define R300_TX_MIRROR_ONCE_TO_BORDER 7 -# define R300_TX_WRAP_S_SHIFT 0 -# define R300_TX_WRAP_S_MASK (7 << 0) -# define R300_TX_WRAP_T_SHIFT 3 -# define R300_TX_WRAP_T_MASK (7 << 3) -# define R300_TX_WRAP_R_SHIFT 6 -# define R300_TX_WRAP_R_MASK (7 << 6) -# define R300_TX_MAG_FILTER_4 (0 << 9) -# define R300_TX_MAG_FILTER_NEAREST (1 << 9) -# define R300_TX_MAG_FILTER_LINEAR (2 << 9) -# define R300_TX_MAG_FILTER_ANISO (3 << 9) -# define R300_TX_MAG_FILTER_MASK (3 << 9) -# define R300_TX_MIN_FILTER_NEAREST (1 << 11) -# define R300_TX_MIN_FILTER_LINEAR (2 << 11) -# define R300_TX_MIN_FILTER_ANISO (3 << 11) -# define R300_TX_MIN_FILTER_MASK (3 << 11) -# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13) -# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13) -# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13) -# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13) -# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) -# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21) -# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21) -# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21) -# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21) -# define R300_TX_MAX_ANISO_MASK (7 << 21) - -#define R300_TX_FILTER1_0 0x4440 -# define R300_CHROMA_KEY_MODE_DISABLE 0 -# define R300_CHROMA_KEY_FORCE 1 -# define R300_CHROMA_KEY_BLEND 2 -# define R300_MC_ROUND_NORMAL (0<<2) -# define R300_MC_ROUND_MPEG4 (1<<2) -# define R300_LOD_BIAS_SHIFT 3 -# define R300_LOD_BIAS_MASK 0x1ff8 -# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) -# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) -# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) -# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) -# define R300_TX_TRI_PERF_0_8 (0<<15) -# define R300_TX_TRI_PERF_1_8 (1<<15) -# define R300_TX_TRI_PERF_1_4 (2<<15) -# define R300_TX_TRI_PERF_3_8 (3<<15) -# define R300_ANISO_THRESHOLD_MASK (7<<17) - -# define R500_MACRO_SWITCH (1<<22) -# define R500_BORDER_FIX (1<<31) - -#define R300_TX_SIZE_0 0x4480 -# define R300_TX_WIDTHMASK_SHIFT 0 -# define R300_TX_WIDTHMASK_MASK (2047 << 0) -# define R300_TX_HEIGHTMASK_SHIFT 11 -# define R300_TX_HEIGHTMASK_MASK (2047 << 11) -# define R300_TX_DEPTHMASK_SHIFT 22 -# define R300_TX_DEPTHMASK_MASK (0xf << 22) -# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 -# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) -# define R300_TX_SIZE_PROJECTED (1<<30) -# define R300_TX_SIZE_TXPITCH_EN (1<<31) -#define R300_TX_FORMAT_0 0x44C0 - /* The interpretation of the format word by Wladimir van der Laan */ - /* The X, Y, Z and W refer to the layout of the components. - They are given meanings as R, G, B and Alpha by the swizzle - specification */ -# define R300_TX_FORMAT_X8 0x0 -# define R500_TX_FORMAT_X1 0x0 // bit set in format 2 -# define R300_TX_FORMAT_X16 0x1 -# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2 -# define R300_TX_FORMAT_Y4X4 0x2 -# define R300_TX_FORMAT_Y8X8 0x3 -# define R300_TX_FORMAT_Y16X16 0x4 -# define R300_TX_FORMAT_Z3Y3X2 0x5 -# define R300_TX_FORMAT_Z5Y6X5 0x6 -# define R300_TX_FORMAT_Z6Y5X5 0x7 -# define R300_TX_FORMAT_Z11Y11X10 0x8 -# define R300_TX_FORMAT_Z10Y11X11 0x9 -# define R300_TX_FORMAT_W4Z4Y4X4 0xA -# define R300_TX_FORMAT_W1Z5Y5X5 0xB -# define R300_TX_FORMAT_W8Z8Y8X8 0xC -# define R300_TX_FORMAT_W2Z10Y10X10 0xD -# define R300_TX_FORMAT_W16Z16Y16X16 0xE -# define R300_TX_FORMAT_DXT1 0xF -# define R300_TX_FORMAT_DXT3 0x10 -# define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ - - /* These two values are wrong, but they're the only values that - * produce any even vaguely correct results. Can r300 only do 16-bit - * depth textures? - */ -# define R300_TX_FORMAT_X24_Y8 0x1e -# define R300_TX_FORMAT_X32 0x1e - - /* 0x16 - some 16 bit green format.. ?? */ -# define R300_TX_FORMAT_3D (1 << 25) -# define R300_TX_FORMAT_CUBIC_MAP (2 << 25) - -# define R300_TX_FORMAT_GAMMA (1 << 21) - - /* gap */ - /* Floating point formats */ - /* Note - hardware supports both 16 and 32 bit floating point */ -# define R300_TX_FORMAT_FL_I16 0x18 -# define R300_TX_FORMAT_FL_I16A16 0x19 -# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A -# define R300_TX_FORMAT_FL_I32 0x1B -# define R300_TX_FORMAT_FL_I32A32 0x1C -# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D - /* alpha modes, convenience mostly */ - /* if you have alpha, pick constant appropriate to the - number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ -# define R300_TX_FORMAT_ALPHA_1CH 0x000 -# define R300_TX_FORMAT_ALPHA_2CH 0x200 -# define R300_TX_FORMAT_ALPHA_4CH 0x600 -# define R300_TX_FORMAT_ALPHA_NONE 0xA00 - /* Swizzling */ - /* constants */ -# define R300_TX_FORMAT_X 0 -# define R300_TX_FORMAT_Y 1 -# define R300_TX_FORMAT_Z 2 -# define R300_TX_FORMAT_W 3 -# define R300_TX_FORMAT_ZERO 4 -# define R300_TX_FORMAT_ONE 5 - /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_Z 6 - /* 2.0*W, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 - -# define R300_TX_FORMAT_B_SHIFT 18 -# define R300_TX_FORMAT_G_SHIFT 15 -# define R300_TX_FORMAT_R_SHIFT 12 -# define R300_TX_FORMAT_A_SHIFT 9 - /* Convenience macro to take care of layout and swizzling */ -# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ - ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ - | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ - | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ - | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ - | (R300_TX_FORMAT_##FMT) \ - ) - /* These can be ORed with result of R300_EASY_TX_FORMAT() - We don't really know what they do. Take values from a - constant color ? */ -# define R300_TX_FORMAT_CONST_X (1<<5) -# define R300_TX_FORMAT_CONST_Y (2<<5) -# define R300_TX_FORMAT_CONST_Z (4<<5) -# define R300_TX_FORMAT_CONST_W (8<<5) - -# define R300_TX_FORMAT_YUV_MODE 0x00800000 - -#define R300_TX_FORMAT2_0 0x4500 /* obvious missing in gap */ -# define R300_TX_PITCHMASK_SHIFT 0 -# define R300_TX_PITCHMASK_MASK (2047 << 0) -# define R500_TXFORMAT_MSB (1 << 14) -# define R500_TXWIDTH_BIT11 (1 << 15) -# define R500_TXHEIGHT_BIT11 (1 << 16) -# define R500_POW2FIX2FLT (1 << 17) -# define R500_SEL_FILTER4_TC0 (0 << 18) -# define R500_SEL_FILTER4_TC1 (1 << 18) -# define R500_SEL_FILTER4_TC2 (2 << 18) -# define R500_SEL_FILTER4_TC3 (3 << 18) - -#define R300_TX_OFFSET_0 0x4540 -#define R300_TX_OFFSET_1 0x4544 -#define R300_TX_OFFSET_2 0x4548 -#define R300_TX_OFFSET_3 0x454C -#define R300_TX_OFFSET_4 0x4550 -#define R300_TX_OFFSET_5 0x4554 -#define R300_TX_OFFSET_6 0x4558 -#define R300_TX_OFFSET_7 0x455C - /* BEGIN: Guess from R200 */ -# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) -# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -# define R300_TXO_MACRO_TILE (1 << 2) -# define R300_TXO_MICRO_TILE_LINEAR (0 << 3) -# define R300_TXO_MICRO_TILE (1 << 3) -# define R300_TXO_MICRO_TILE_SQUARE (2 << 3) -# define R300_TXO_OFFSET_MASK 0xffffffe0 -# define R300_TXO_OFFSET_SHIFT 5 - /* END: Guess from R200 */ - -/* 32 bit chroma key */ -#define R300_TX_CHROMA_KEY_0 0x4580 -#define R300_TX_CHROMA_KEY_1 0x4584 -#define R300_TX_CHROMA_KEY_2 0x4588 -#define R300_TX_CHROMA_KEY_3 0x458c -#define R300_TX_CHROMA_KEY_4 0x4590 -#define R300_TX_CHROMA_KEY_5 0x4594 -#define R300_TX_CHROMA_KEY_6 0x4598 -#define R300_TX_CHROMA_KEY_7 0x459c -#define R300_TX_CHROMA_KEY_8 0x45a0 -#define R300_TX_CHROMA_KEY_9 0x45a4 -#define R300_TX_CHROMA_KEY_10 0x45a8 -#define R300_TX_CHROMA_KEY_11 0x45ac -#define R300_TX_CHROMA_KEY_12 0x45b0 -#define R300_TX_CHROMA_KEY_13 0x45b4 -#define R300_TX_CHROMA_KEY_14 0x45b8 -#define R300_TX_CHROMA_KEY_15 0x45bc -/* ff00ff00 == { 0, 1.0, 0, 1.0 } */ - -/* Border Color */ -#define R300_TX_BORDER_COLOR_0 0x45c0 -#define R300_TX_BORDER_COLOR_1 0x45c4 -#define R300_TX_BORDER_COLOR_2 0x45c8 -#define R300_TX_BORDER_COLOR_3 0x45cc -#define R300_TX_BORDER_COLOR_4 0x45d0 -#define R300_TX_BORDER_COLOR_5 0x45d4 -#define R300_TX_BORDER_COLOR_6 0x45d8 -#define R300_TX_BORDER_COLOR_7 0x45dc -#define R300_TX_BORDER_COLOR_8 0x45e0 -#define R300_TX_BORDER_COLOR_9 0x45e4 -#define R300_TX_BORDER_COLOR_10 0x45e8 -#define R300_TX_BORDER_COLOR_11 0x45ec -#define R300_TX_BORDER_COLOR_12 0x45f0 -#define R300_TX_BORDER_COLOR_13 0x45f4 -#define R300_TX_BORDER_COLOR_14 0x45f8 -#define R300_TX_BORDER_COLOR_15 0x45fc - - -/* END: Texture specification */ - -/* BEGIN: Fragment program instruction set */ - -/* Fragment programs are written directly into register space. - * There are separate instruction streams for texture instructions and ALU - * instructions. - * In order to synchronize these streams, the program is divided into up - * to 4 nodes. Each node begins with a number of TEX operations, followed - * by a number of ALU operations. - * The first node can have zero TEX ops, all subsequent nodes must have at - * least - * one TEX ops. - * All nodes must have at least one ALU op. - * - * The index of the last node is stored in PFS_CNTL_0: A value of 0 means - * 1 node, a value of 3 means 4 nodes. - * The total amount of instructions is defined in PFS_CNTL_2. The offsets are - * offsets into the respective instruction streams, while *_END points to the - * last instruction relative to this offset. - */ -#define R300_US_CONFIG 0x4600 -# define R300_PFS_CNTL_LAST_NODES_SHIFT 0 -# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) -# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) -#define R300_US_PIXSIZE 0x4604 -/* There is an unshifted value here which has so far always been equal to the - * index of the highest used temporary register. - */ -#define R300_US_CODE_OFFSET 0x4608 -# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 -# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) -# define R300_PFS_CNTL_ALU_END_SHIFT 6 -# define R300_PFS_CNTL_ALU_END_MASK (63 << 6) -# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 13 -# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13) -# define R300_PFS_CNTL_TEX_END_SHIFT 18 -# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) -# define R400_PFS_CNTL_TEX_OFFSET_MSB_SHIFT 24 -# define R400_PFS_CNTL_TEX_OFFSET_MSB_MASK (0xf << 24) -# define R400_PFS_CNTL_TEX_END_MSB_SHIFT 28 -# define R400_PFS_CNTL_TEX_END_MSB_MASK (0xf << 28) - -/* gap */ - -/* Nodes are stored backwards. The last active node is always stored in - * PFS_NODE_3. - * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The - * first node is stored in NODE_2, the second node is stored in NODE_3. - * - * Offsets are relative to the master offset from PFS_CNTL_2. - */ -#define R300_US_CODE_ADDR_0 0x4610 -#define R300_US_CODE_ADDR_1 0x4614 -#define R300_US_CODE_ADDR_2 0x4618 -#define R300_US_CODE_ADDR_3 0x461C -# define R300_ALU_START_SHIFT 0 -# define R300_ALU_START_MASK (63 << 0) -# define R300_ALU_SIZE_SHIFT 6 -# define R300_ALU_SIZE_MASK (63 << 6) -# define R300_TEX_START_SHIFT 12 -# define R300_TEX_START_MASK (31 << 12) -# define R300_TEX_SIZE_SHIFT 17 -# define R300_TEX_SIZE_MASK (31 << 17) -# define R300_RGBA_OUT (1 << 22) -# define R300_W_OUT (1 << 23) -# define R400_TEX_START_MSB_SHIFT 24 -# define R400_TEX_START_MSG_MASK (0xf << 24) -# define R400_TEX_SIZE_MSB_SHIFT 28 -# define R400_TEX_SIZE_MSG_MASK (0xf << 28) - -/* TEX - * As far as I can tell, texture instructions cannot write into output - * registers directly. A subsequent ALU instruction is always necessary, - * even if it's just MAD o0, r0, 1, 0 - */ -#define R300_US_TEX_INST_0 0x4620 -# define R300_SRC_ADDR_SHIFT 0 -# define R300_SRC_ADDR_MASK (31 << 0) -# define R300_DST_ADDR_SHIFT 6 -# define R300_DST_ADDR_MASK (31 << 6) -# define R300_TEX_ID_SHIFT 11 -# define R300_TEX_ID_MASK (15 << 11) -# define R300_TEX_INST_SHIFT 15 -# define R300_TEX_OP_NOP 0 -# define R300_TEX_OP_LD 1 -# define R300_TEX_OP_KIL 2 -# define R300_TEX_OP_TXP 3 -# define R300_TEX_OP_TXB 4 -# define R300_TEX_INST_MASK (7 << 15) -# define R400_SRC_ADDR_EXT_BIT (1 << 19) -# define R400_DST_ADDR_EXT_BIT (1 << 20) - -/* Output format from the unfied shader */ -#define R300_US_OUT_FMT 0x46A4 -# define R300_US_OUT_FMT_C4_8 (0 << 0) -# define R300_US_OUT_FMT_C4_10 (1 << 0) -# define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0) -# define R300_US_OUT_FMT_C_16 (3 << 0) -# define R300_US_OUT_FMT_C2_16 (4 << 0) -# define R300_US_OUT_FMT_C4_16 (5 << 0) -# define R300_US_OUT_FMT_C_16_MPEG (6 << 0) -# define R300_US_OUT_FMT_C2_16_MPEG (7 << 0) -# define R300_US_OUT_FMT_C2_4 (8 << 0) -# define R300_US_OUT_FMT_C_3_3_2 (9 << 0) -# define R300_US_OUT_FMT_C_6_5_6 (10 << 0) -# define R300_US_OUT_FMT_C_11_11_10 (11 << 0) -# define R300_US_OUT_FMT_C_10_11_11 (12 << 0) -# define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0) -/* reserved */ -# define R300_US_OUT_FMT_UNUSED (15 << 0) -# define R300_US_OUT_FMT_C_16_FP (16 << 0) -# define R300_US_OUT_FMT_C2_16_FP (17 << 0) -# define R300_US_OUT_FMT_C4_16_FP (18 << 0) -# define R300_US_OUT_FMT_C_32_FP (19 << 0) -# define R300_US_OUT_FMT_C2_32_FP (20 << 0) -# define R300_US_OUT_FMT_C4_32_FP (20 << 0) - -/* ALU - * The ALU instructions register blocks are enumerated according to the order - * in which fglrx. I assume there is space for 64 instructions, since - * each block has space for a maximum of 64 DWORDs, and this matches reported - * native limits. - * - * The basic functional block seems to be one MAD for each color and alpha, - * and an adder that adds all components after the MUL. - * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands - * - DP4: Use OUTC_DP4, OUTA_DP4 - * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands - * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands - * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 - * - CMP: If ARG2 < 0, return ARG1, else return ARG0 - * - FLR: use FRC+MAD - * - XPD: use MAD+MAD - * - SGE, SLT: use MAD+CMP - * - RSQ: use ABS modifier for argument - * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation - * (e.g. RCP) into color register - * - apparently, there's no quick DST operation - * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" - * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" - * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" - * - * Operand selection - * First stage selects three sources from the available registers and - * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). - * fglrx sorts the three source fields: Registers before constants, - * lower indices before higher indices; I do not know whether this is - * necessary. - * - * fglrx fills unused sources with "read constant 0" - * According to specs, you cannot select more than two different constants. - * - * Second stage selects the operands from the sources. This is defined in - * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants - * zero and one. - * Swizzling and negation happens in this stage, as well. - * - * Important: Color and alpha seem to be mostly separate, i.e. their sources - * selection appears to be fully independent (the register storage is probably - * physically split into a color and an alpha section). - * However (because of the apparent physical split), there is some interaction - * WRT swizzling. If, for example, you want to load an R component into an - * Alpha operand, this R component is taken from a *color* source, not from - * an alpha source. The corresponding register doesn't even have to appear in - * the alpha sources list. (I hope this all makes sense to you) - * - * Destination selection - * The destination register index is in FPI1 (color) and FPI3 (alpha) - * together with enable bits. - * There are separate enable bits for writing into temporary registers - * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_* - * /DSTA_OUTPUT). You can write to both at once, or not write at all (the - * same index must be used for both). - * - * Note: There is a special form for LRP - * - Argument order is the same as in ARB_fragment_program. - * - Operation is MAD - * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP - * - Set FPI0/FPI2_SPECIAL_LRP - * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD - */ -#define R300_US_ALU_RGB_ADDR_0 0x46C0 -# define R300_ALU_SRC0C_SHIFT 0 -# define R300_ALU_SRC0C_MASK (31 << 0) -# define R300_ALU_SRC0C_CONST (1 << 5) -# define R300_ALU_SRC1C_SHIFT 6 -# define R300_ALU_SRC1C_MASK (31 << 6) -# define R300_ALU_SRC1C_CONST (1 << 11) -# define R300_ALU_SRC2C_SHIFT 12 -# define R300_ALU_SRC2C_MASK (31 << 12) -# define R300_ALU_SRC2C_CONST (1 << 17) -# define R300_ALU_SRC_MASK 0x0003ffff -# define R300_ALU_DSTC_SHIFT 18 -# define R300_ALU_DSTC_MASK (31 << 18) -# define R300_ALU_DSTC_REG_MASK_SHIFT 23 -# define R300_ALU_DSTC_REG_X (1 << 23) -# define R300_ALU_DSTC_REG_Y (1 << 24) -# define R300_ALU_DSTC_REG_Z (1 << 25) -# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26 -# define R300_ALU_DSTC_OUTPUT_X (1 << 26) -# define R300_ALU_DSTC_OUTPUT_Y (1 << 27) -# define R300_ALU_DSTC_OUTPUT_Z (1 << 28) -# define R300_RGB_TARGET(x) ((x) << 29) - -#define R300_US_ALU_ALPHA_ADDR_0 0x47C0 -# define R300_ALU_SRC0A_SHIFT 0 -# define R300_ALU_SRC0A_MASK (31 << 0) -# define R300_ALU_SRC0A_CONST (1 << 5) -# define R300_ALU_SRC1A_SHIFT 6 -# define R300_ALU_SRC1A_MASK (31 << 6) -# define R300_ALU_SRC1A_CONST (1 << 11) -# define R300_ALU_SRC2A_SHIFT 12 -# define R300_ALU_SRC2A_MASK (31 << 12) -# define R300_ALU_SRC2A_CONST (1 << 17) -# define R300_ALU_SRC_MASK 0x0003ffff -# define R300_ALU_DSTA_SHIFT 18 -# define R300_ALU_DSTA_MASK (31 << 18) -# define R300_ALU_DSTA_REG (1 << 23) -# define R300_ALU_DSTA_OUTPUT (1 << 24) -# define R300_ALU_DSTA_DEPTH (1 << 27) -# define R300_ALPHA_TARGET(x) ((x) << 25) - -#define R300_US_ALU_RGB_INST_0 0x48C0 -# define R300_ALU_ARGC_SRC0C_XYZ 0 -# define R300_ALU_ARGC_SRC0C_XXX 1 -# define R300_ALU_ARGC_SRC0C_YYY 2 -# define R300_ALU_ARGC_SRC0C_ZZZ 3 -# define R300_ALU_ARGC_SRC1C_XYZ 4 -# define R300_ALU_ARGC_SRC1C_XXX 5 -# define R300_ALU_ARGC_SRC1C_YYY 6 -# define R300_ALU_ARGC_SRC1C_ZZZ 7 -# define R300_ALU_ARGC_SRC2C_XYZ 8 -# define R300_ALU_ARGC_SRC2C_XXX 9 -# define R300_ALU_ARGC_SRC2C_YYY 10 -# define R300_ALU_ARGC_SRC2C_ZZZ 11 -# define R300_ALU_ARGC_SRC0A 12 -# define R300_ALU_ARGC_SRC1A 13 -# define R300_ALU_ARGC_SRC2A 14 -# define R300_ALU_ARGC_SRCP_XYZ 15 -# define R300_ALU_ARGC_SRCP_XXX 16 -# define R300_ALU_ARGC_SRCP_YYY 17 -# define R300_ALU_ARGC_SRCP_ZZZ 18 -# define R300_ALU_ARGC_SRCP_WWW 19 -# define R300_ALU_ARGC_ZERO 20 -# define R300_ALU_ARGC_ONE 21 -# define R300_ALU_ARGC_HALF 22 -# define R300_ALU_ARGC_SRC0C_YZX 23 -# define R300_ALU_ARGC_SRC1C_YZX 24 -# define R300_ALU_ARGC_SRC2C_YZX 25 -# define R300_ALU_ARGC_SRC0C_ZXY 26 -# define R300_ALU_ARGC_SRC1C_ZXY 27 -# define R300_ALU_ARGC_SRC2C_ZXY 28 -# define R300_ALU_ARGC_SRC0CA_WZY 29 -# define R300_ALU_ARGC_SRC1CA_WZY 30 -# define R300_ALU_ARGC_SRC2CA_WZY 31 - -# define R300_ALU_ARG0C_SHIFT 0 -# define R300_ALU_ARG0C_MASK (31 << 0) -# define R300_ALU_ARG0C_NOP (0 << 5) -# define R300_ALU_ARG0C_NEG (1 << 5) -# define R300_ALU_ARG0C_ABS (2 << 5) -# define R300_ALU_ARG0C_NAB (3 << 5) -# define R300_ALU_ARG1C_SHIFT 7 -# define R300_ALU_ARG1C_MASK (31 << 7) -# define R300_ALU_ARG1C_NOP (0 << 12) -# define R300_ALU_ARG1C_NEG (1 << 12) -# define R300_ALU_ARG1C_ABS (2 << 12) -# define R300_ALU_ARG1C_NAB (3 << 12) -# define R300_ALU_ARG2C_SHIFT 14 -# define R300_ALU_ARG2C_MASK (31 << 14) -# define R300_ALU_ARG2C_NOP (0 << 19) -# define R300_ALU_ARG2C_NEG (1 << 19) -# define R300_ALU_ARG2C_ABS (2 << 19) -# define R300_ALU_ARG2C_NAB (3 << 19) -# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) -# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) -# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) -# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) - -# define R300_ALU_OUTC_MAD (0 << 23) -# define R300_ALU_OUTC_DP3 (1 << 23) -# define R300_ALU_OUTC_DP4 (2 << 23) -# define R300_ALU_OUTC_D2A (3 << 23) -# define R300_ALU_OUTC_MIN (4 << 23) -# define R300_ALU_OUTC_MAX (5 << 23) -# define R300_ALU_OUTC_CND (7 << 23) -# define R300_ALU_OUTC_CMP (8 << 23) -# define R300_ALU_OUTC_FRC (9 << 23) -# define R300_ALU_OUTC_REPL_ALPHA (10 << 23) - -# define R300_ALU_OUTC_MOD_NOP (0 << 27) -# define R300_ALU_OUTC_MOD_MUL2 (1 << 27) -# define R300_ALU_OUTC_MOD_MUL4 (2 << 27) -# define R300_ALU_OUTC_MOD_MUL8 (3 << 27) -# define R300_ALU_OUTC_MOD_DIV2 (4 << 27) -# define R300_ALU_OUTC_MOD_DIV4 (5 << 27) -# define R300_ALU_OUTC_MOD_DIV8 (6 << 27) - -# define R300_ALU_OUTC_CLAMP (1 << 30) -# define R300_ALU_INSERT_NOP (1 << 31) - -#define R300_US_ALU_ALPHA_INST_0 0x49C0 -# define R300_ALU_ARGA_SRC0C_X 0 -# define R300_ALU_ARGA_SRC0C_Y 1 -# define R300_ALU_ARGA_SRC0C_Z 2 -# define R300_ALU_ARGA_SRC1C_X 3 -# define R300_ALU_ARGA_SRC1C_Y 4 -# define R300_ALU_ARGA_SRC1C_Z 5 -# define R300_ALU_ARGA_SRC2C_X 6 -# define R300_ALU_ARGA_SRC2C_Y 7 -# define R300_ALU_ARGA_SRC2C_Z 8 -# define R300_ALU_ARGA_SRC0A 9 -# define R300_ALU_ARGA_SRC1A 10 -# define R300_ALU_ARGA_SRC2A 11 -# define R300_ALU_ARGA_SRCP_X 12 -# define R300_ALU_ARGA_SRCP_Y 13 -# define R300_ALU_ARGA_SRCP_Z 14 -# define R300_ALU_ARGA_SRCP_W 15 - -# define R300_ALU_ARGA_ZERO 16 -# define R300_ALU_ARGA_ONE 17 -# define R300_ALU_ARGA_HALF 18 -# define R300_ALU_ARG0A_SHIFT 0 -# define R300_ALU_ARG0A_MASK (31 << 0) -# define R300_ALU_ARG0A_NOP (0 << 5) -# define R300_ALU_ARG0A_NEG (1 << 5) -# define R300_ALU_ARG0A_ABS (2 << 5) -# define R300_ALU_ARG0A_NAB (3 << 5) -# define R300_ALU_ARG1A_SHIFT 7 -# define R300_ALU_ARG1A_MASK (31 << 7) -# define R300_ALU_ARG1A_NOP (0 << 12) -# define R300_ALU_ARG1A_NEG (1 << 12) -# define R300_ALU_ARG1A_ABS (2 << 12) -# define R300_ALU_ARG1A_NAB (3 << 12) -# define R300_ALU_ARG2A_SHIFT 14 -# define R300_ALU_ARG2A_MASK (31 << 14) -# define R300_ALU_ARG2A_NOP (0 << 19) -# define R300_ALU_ARG2A_NEG (1 << 19) -# define R300_ALU_ARG2A_ABS (2 << 19) -# define R300_ALU_ARG2A_NAB (3 << 19) -# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) -# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) -# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) -# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) - -# define R300_ALU_OUTA_MAD (0 << 23) -# define R300_ALU_OUTA_DP4 (1 << 23) -# define R300_ALU_OUTA_MIN (2 << 23) -# define R300_ALU_OUTA_MAX (3 << 23) -# define R300_ALU_OUTA_CND (5 << 23) -# define R300_ALU_OUTA_CMP (6 << 23) -# define R300_ALU_OUTA_FRC (7 << 23) -# define R300_ALU_OUTA_EX2 (8 << 23) -# define R300_ALU_OUTA_LG2 (9 << 23) -# define R300_ALU_OUTA_RCP (10 << 23) -# define R300_ALU_OUTA_RSQ (11 << 23) - -# define R300_ALU_OUTA_MOD_NOP (0 << 27) -# define R300_ALU_OUTA_MOD_MUL2 (1 << 27) -# define R300_ALU_OUTA_MOD_MUL4 (2 << 27) -# define R300_ALU_OUTA_MOD_MUL8 (3 << 27) -# define R300_ALU_OUTA_MOD_DIV2 (4 << 27) -# define R300_ALU_OUTA_MOD_DIV4 (5 << 27) -# define R300_ALU_OUTA_MOD_DIV8 (6 << 27) - -# define R300_ALU_OUTA_CLAMP (1 << 30) -/* END: Fragment program instruction set */ - -/* R4xx extended fragment shader registers. */ -#define R400_US_ALU_EXT_ADDR_0 0x4ac0 /* up to 63 (0x4bbc) */ -# define R400_ADDR_EXT_RGB_MSB_BIT(x) (1 << (x)) -# define R400_ADDRD_EXT_RGB_MSB_BIT 0x08 -# define R400_ADDR_EXT_A_MSB_BIT(x) (1 << ((x) + 4)) -# define R400_ADDRD_EXT_A_MSB_BIT 0x80 - -#define R400_US_CODE_BANK 0x46b8 -# define R400_BANK_SHIFT 0 -# define R400_BANK_MASK 0xf -# define R400_R390_MODE_ENABLE (1 << 4) -#define R400_US_CODE_EXT 0x46bc -# define R400_ALU_OFFSET_MSB_SHIFT 0 -# define R400_ALU_OFFSET_MSB_MASK (0x7 << 0) -# define R400_ALU_SIZE_MSB_SHIFT 3 -# define R400_ALU_SIZE_MSB_MASK (0x7 << 3) -# define R400_ALU_START0_MSB_SHIFT 6 -# define R400_ALU_START0_MSB_MASK (0x7 << 6) -# define R400_ALU_SIZE0_MSB_SHIFT 9 -# define R400_ALU_SIZE0_MSB_MASK (0x7 << 9) -# define R400_ALU_START1_MSB_SHIFT 12 -# define R400_ALU_START1_MSB_MASK (0x7 << 12) -# define R400_ALU_SIZE1_MSB_SHIFT 15 -# define R400_ALU_SIZE1_MSB_MASK (0x7 << 15) -# define R400_ALU_START2_MSB_SHIFT 18 -# define R400_ALU_START2_MSB_MASK (0x7 << 18) -# define R400_ALU_SIZE2_MSB_SHIFT 21 -# define R400_ALU_SIZE2_MSB_MASK (0x7 << 21) -# define R400_ALU_START3_MSB_SHIFT 24 -# define R400_ALU_START3_MSB_MASK (0x7 << 24) -# define R400_ALU_SIZE3_MSB_SHIFT 27 -# define R400_ALU_SIZE3_MSB_MASK (0x7 << 27) -/* END: R4xx extended fragment shader registers. */ - -/* Fog: Fog Blending Enable */ -#define R300_FG_FOG_BLEND 0x4bc0 -# define R300_FG_FOG_BLEND_DISABLE (0 << 0) -# define R300_FG_FOG_BLEND_ENABLE (1 << 0) -# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1) -# define R300_FG_FOG_BLEND_FN_EXP (1 << 1) -# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1) -# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1) -# define R300_FG_FOG_BLEND_FN_MASK (3 << 1) - -/* Fog: Red Component of Fog Color */ -#define R300_FG_FOG_COLOR_R 0x4bc8 -/* Fog: Green Component of Fog Color */ -#define R300_FG_FOG_COLOR_G 0x4bcc -/* Fog: Blue Component of Fog Color */ -#define R300_FG_FOG_COLOR_B 0x4bd0 -# define R300_FG_FOG_COLOR_MASK 0x000003ff - -/* Fog: Constant Factor for Fog Blending */ -#define R300_FG_FOG_FACTOR 0x4bc4 -# define FG_FOG_FACTOR_MASK 0x000003ff - -/* Fog: Alpha function */ -#define R300_FG_ALPHA_FUNC 0x4bd4 -# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff -# define R300_FG_ALPHA_FUNC_NEVER (0 << 8) -# define R300_FG_ALPHA_FUNC_LESS (1 << 8) -# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8) -# define R300_FG_ALPHA_FUNC_LE (3 << 8) -# define R300_FG_ALPHA_FUNC_GREATER (4 << 8) -# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8) -# define R300_FG_ALPHA_FUNC_GE (6 << 8) -# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8) -# define R300_ALPHA_TEST_OP_MASK (7 << 8) -# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11) -# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11) - -# define R500_FG_ALPHA_FUNC_10BIT (0 << 12) -# define R500_FG_ALPHA_FUNC_8BIT (1 << 12) - -# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16) -# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16) -# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17) -# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17) - -# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20) -# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20) - -# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24) -# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */ -# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25) -# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25) - -# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28) -# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28) - - -/* Fog: Where does the depth come from? */ -#define R300_FG_DEPTH_SRC 0x4bd8 -# define R300_FG_DEPTH_SRC_SCAN (0 << 0) -# define R300_FG_DEPTH_SRC_SHADER (1 << 0) - -/* Fog: Alpha Compare Value */ -#define R500_FG_ALPHA_VALUE 0x4be0 -# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff - -#define RV530_FG_ZBREG_DEST 0x4be8 -# define RV530_FG_ZBREG_DEST_PIPE_SELECT_0 (1 << 0) -# define RV530_FG_ZBREG_DEST_PIPE_SELECT_1 (1 << 1) -# define RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL (3 << 0) - -/* gap */ - -/* Fragment program parameters in 7.16 floating point */ -#define R300_PFS_PARAM_0_X 0x4C00 -#define R300_PFS_PARAM_0_Y 0x4C04 -#define R300_PFS_PARAM_0_Z 0x4C08 -#define R300_PFS_PARAM_0_W 0x4C0C -/* last consts */ -#define R300_PFS_PARAM_31_X 0x4DF0 -#define R300_PFS_PARAM_31_Y 0x4DF4 -#define R300_PFS_PARAM_31_Z 0x4DF8 -#define R300_PFS_PARAM_31_W 0x4DFC - -/* Unpipelined. */ -#define R300_RB3D_CCTL 0x4e00 -# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5) -# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5) -# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5) -# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5) -# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7) -# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7) -# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9) -# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9) -# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10) -# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10) -/* reserved */ -# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12) -# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12) -# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13) -# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13) -# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14) -# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14) - - -/* Notes: - * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in - * the application - * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND - * are set to the same - * function (both registers are always set up completely in any case) - * - Most blend flags are simply copied from R200 and not tested yet - */ -#define R300_RB3D_CBLEND 0x4E04 -#define R300_RB3D_ABLEND 0x4E08 -/* the following only appear in CBLEND */ -# define R300_ALPHA_BLEND_ENABLE (1 << 0) -# define R300_SEPARATE_ALPHA_ENABLE (1 << 1) -# define R300_READ_ENABLE (1 << 2) -# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3) -# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3) - -/* the following are shared between CBLEND and ABLEND */ -# define R300_FCN_MASK (3 << 12) -# define R300_COMB_FCN_ADD_CLAMP (0 << 12) -# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) -# define R300_COMB_FCN_SUB_CLAMP (2 << 12) -# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) -# define R300_COMB_FCN_MIN (4 << 12) -# define R300_COMB_FCN_MAX (5 << 12) -# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) -# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) -# define R300_BLEND_GL_ZERO (32) -# define R300_BLEND_GL_ONE (33) -# define R300_BLEND_GL_SRC_COLOR (34) -# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) -# define R300_BLEND_GL_DST_COLOR (36) -# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) -# define R300_BLEND_GL_SRC_ALPHA (38) -# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) -# define R300_BLEND_GL_DST_ALPHA (40) -# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) -# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) -# define R300_BLEND_GL_CONST_COLOR (43) -# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) -# define R300_BLEND_GL_CONST_ALPHA (45) -# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) -# define R300_BLEND_MASK (63) -# define R300_SRC_BLEND_SHIFT (16) -# define R300_DST_BLEND_SHIFT (24) - -/* Constant color used by the blender. Pipelined through the blender. - * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE, - * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead. - */ -#define R300_RB3D_BLEND_COLOR 0x4E10 - - -/* 3D Color Channel Mask. If all the channels used in the current color format - * are disabled, then the cb will discard all the incoming quads. Pipelined - * through the blender. - */ -#define RB3D_COLOR_CHANNEL_MASK 0x4E0C -# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 (1 << 0) -# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1) -# define RB3D_COLOR_CHANNEL_MASK_RED_MASK0 (1 << 2) -# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3) -# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1 (1 << 4) -# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5) -# define RB3D_COLOR_CHANNEL_MASK_RED_MASK1 (1 << 6) -# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7) -# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2 (1 << 8) -# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9) -# define RB3D_COLOR_CHANNEL_MASK_RED_MASK2 (1 << 10) -# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11) -# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3 (1 << 12) -# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13) -# define RB3D_COLOR_CHANNEL_MASK_RED_MASK3 (1 << 14) -# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15) - -/* Clear color that is used when the color mask is set to 00. Unpipelined. - * Program this register with a 32-bit value in ARGB8888 or ARGB2101010 - * formats, ignoring the fields. - */ -#define RB3D_COLOR_CLEAR_VALUE 0x4e14 - -/* gap */ - -/* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */ -#define RB3D_CLRCMP_CLR 0x4e20 - -/* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */ -#define RB3D_CLRCMP_MSK 0x4e24 - -/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */ -#define R300_RB3D_COLOROFFSET0 0x4E28 -# define R300_COLOROFFSET_MASK 0xFFFFFFE0 -/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */ -#define R300_RB3D_COLOROFFSET1 0x4E2C -/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */ -#define R300_RB3D_COLOROFFSET2 0x4E30 -/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */ -#define R300_RB3D_COLOROFFSET3 0x4E34 - -/* Color buffer format and tiling control for all the multibuffers and the - * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any - * of the registers are changed. - * - * Bit 16: Larger tiles - * Bit 17: 4x2 tiles - * Bit 18: Extremely weird tile like, but some pixels duplicated? - */ -#define R300_RB3D_COLORPITCH0 0x4E38 -# define R300_COLORPITCH_MASK 0x00003FFE -# define R300_COLOR_TILE_DISABLE (0 << 16) -# define R300_COLOR_TILE_ENABLE (1 << 16) -# define R300_COLOR_MICROTILE_DISABLE (0 << 17) -# define R300_COLOR_MICROTILE_ENABLE (1 << 17) -# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */ -# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19) -# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19) -# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19) -# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19) -# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21) -# define R500_COLOR_FORMAT_UV1010 (1 << 21) -# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */ -# define R300_COLOR_FORMAT_ARGB1555 (3 << 21) -# define R300_COLOR_FORMAT_RGB565 (4 << 21) -# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21) -# define R300_COLOR_FORMAT_ARGB8888 (6 << 21) -# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21) -/* reserved */ -# define R300_COLOR_FORMAT_I8 (9 << 21) -# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21) -# define R300_COLOR_FORMAT_VYUY (11 << 21) -# define R300_COLOR_FORMAT_YVYU (12 << 21) -# define R300_COLOR_FORMAT_UV88 (13 << 21) -# define R500_COLOR_FORMAT_I10 (14 << 21) -# define R300_COLOR_FORMAT_ARGB4444 (15 << 21) -#define R300_RB3D_COLORPITCH1 0x4E3C -#define R300_RB3D_COLORPITCH2 0x4E40 -#define R300_RB3D_COLORPITCH3 0x4E44 - -/* gap */ - -/* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then - * a flush or free will not occur upon a write to this register, but a sync - * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE - * are zero but DC_FINISH is one, then a sync will be sent immediately -- the - * cb will not wait for all the previous operations to complete before sending - * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to - * zero. - * - * Set to 0A before 3D operations, set to 02 afterwards. - */ -#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4) -# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4) - -#define R300_RB3D_DITHER_CTL 0x4E50 -# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0) -# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0) -# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0) -/* reserved */ -# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2) -# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2) -# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2) -/* reserved */ - -/* Resolve buffer destination address. The cache must be empty before changing - * this register if the cb is in resolve mode. Unpipelined - */ -#define R300_RB3D_AARESOLVE_OFFSET 0x4e80 -# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5 -# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */ - -/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before - * changing this register if the cb is in resolve mode. Unpipelined - */ -#define R300_RB3D_AARESOLVE_PITCH 0x4e84 -# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1 -# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */ - -/* Resolve Buffer Control. Unpipelined */ -#define R300_RB3D_AARESOLVE_CTL 0x4e88 -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0) -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0) -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1) -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1) -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2) -# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2) - - -/* Discard src pixels less than or equal to threshold. */ -#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0 -/* Discard src pixels greater than or equal to threshold. */ -#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000 - -/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */ -#define R300_RB3D_ROPCNTL 0x4e18 -# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004 -# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8) -# define R300_RB3D_ROPCNTL_ROP_SHIFT 8 - -/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */ -#define R300_RB3D_CLRCMP_FLIPE 0x4e1c - -/* Sets the fifo sizes */ -#define R500_RB3D_FIFO_SIZE 0x4ef4 -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0) - -/* Constant color used by the blender. Pipelined through the blender. */ -#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 -# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff -# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0 -# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000 -# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16 - -/* Constant color used by the blender. Pipelined through the blender. */ -#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc -# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff -# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0 -# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000 -# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16 - -/* gap */ -/* There seems to be no "write only" setting, so use Z-test = ALWAYS - * for this. - * Bit (1<<8) is the "test" bit. so plain write is 6 - vd - */ -#define R300_ZB_CNTL 0x4F00 -# define R300_STENCIL_ENABLE (1 << 0) -# define R300_Z_ENABLE (1 << 1) -# define R300_Z_WRITE_ENABLE (1 << 2) -# define R300_Z_SIGNED_COMPARE (1 << 3) -# define R300_STENCIL_FRONT_BACK (1 << 4) -# define R400_ZSIGNED_MAGNITUDE (1 << 5) -# define R500_STENCIL_REFMASK_FRONT_BACK (1 << 6) - -#define R300_ZB_ZSTENCILCNTL 0x4f04 - /* functions */ -# define R300_ZS_NEVER 0 -# define R300_ZS_LESS 1 -# define R300_ZS_LEQUAL 2 -# define R300_ZS_EQUAL 3 -# define R300_ZS_GEQUAL 4 -# define R300_ZS_GREATER 5 -# define R300_ZS_NOTEQUAL 6 -# define R300_ZS_ALWAYS 7 -# define R300_ZS_MASK 7 - /* operations */ -# define R300_ZS_KEEP 0 -# define R300_ZS_ZERO 1 -# define R300_ZS_REPLACE 2 -# define R300_ZS_INCR 3 -# define R300_ZS_DECR 4 -# define R300_ZS_INVERT 5 -# define R300_ZS_INCR_WRAP 6 -# define R300_ZS_DECR_WRAP 7 -# define R300_Z_FUNC_SHIFT 0 - /* front and back refer to operations done for front - and back faces, i.e. separate stencil function support */ -# define R300_S_FRONT_FUNC_SHIFT 3 -# define R300_S_FRONT_SFAIL_OP_SHIFT 6 -# define R300_S_FRONT_ZPASS_OP_SHIFT 9 -# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 -# define R300_S_BACK_FUNC_SHIFT 15 -# define R300_S_BACK_SFAIL_OP_SHIFT 18 -# define R300_S_BACK_ZPASS_OP_SHIFT 21 -# define R300_S_BACK_ZFAIL_OP_SHIFT 24 - -#define R300_ZB_STENCILREFMASK 0x4f08 -# define R300_STENCILREF_SHIFT 0 -# define R300_STENCILREF_MASK 0x000000ff -# define R300_STENCILMASK_SHIFT 8 -# define R300_STENCILMASK_MASK 0x0000ff00 -# define R300_STENCILWRITEMASK_SHIFT 16 -# define R300_STENCILWRITEMASK_MASK 0x00ff0000 - -/* gap */ - -#define R300_ZB_FORMAT 0x4f10 -# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) -# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) -# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) -/* reserved up to (15 << 0) */ -# define R300_INVERT_13E3_LEADING_ONES (0 << 4) -# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) - -#define R300_ZB_ZTOP 0x4F14 -# define R300_ZTOP_DISABLE (0 << 0) -# define R300_ZTOP_ENABLE (1 << 0) - -/* gap */ - -#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) - -#define R300_ZB_BW_CNTL 0x4f1c -# define R300_HIZ_DISABLE (0 << 0) -# define R300_HIZ_ENABLE (1 << 0) -# define R300_HIZ_MIN (0 << 1) -# define R300_HIZ_MAX (1 << 1) -# define R300_FAST_FILL_DISABLE (0 << 2) -# define R300_FAST_FILL_ENABLE (1 << 2) -# define R300_RD_COMP_DISABLE (0 << 3) -# define R300_RD_COMP_ENABLE (1 << 3) -# define R300_WR_COMP_DISABLE (0 << 4) -# define R300_WR_COMP_ENABLE (1 << 4) -# define R300_ZB_CB_CLEAR_RMW (0 << 5) -# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) -# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) -# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) - -# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) -# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) -# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) -# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) - -# define R500_BMASK_ENABLE (0 << 10) -# define R500_BMASK_DISABLE (1 << 10) -# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) -# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) -# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) -# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) -# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) -# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) -# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) -# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) -# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) -# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) -# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) -# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) -# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) -# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) -# define R500_PEQ_PACKING_DISABLE (0 << 18) -# define R500_PEQ_PACKING_ENABLE (1 << 18) -# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) -# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) - - -/* gap */ - -/* Z Buffer Address Offset. - * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. - */ -#define R300_ZB_DEPTHOFFSET 0x4f20 - -/* Z Buffer Pitch and Endian Control */ -#define R300_ZB_DEPTHPITCH 0x4f24 -# define R300_DEPTHPITCH_MASK 0x00003FFC -# define R300_DEPTHMACROTILE_DISABLE (0 << 16) -# define R300_DEPTHMACROTILE_ENABLE (1 << 16) -# define R300_DEPTHMICROTILE_LINEAR (0 << 17) -# define R300_DEPTHMICROTILE_TILED (1 << 17) -# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) -# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) -# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) -# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) -# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) - -/* Z Buffer Clear Value */ -#define R300_ZB_DEPTHCLEARVALUE 0x4f28 - -#define R300_ZB_ZMASK_OFFSET 0x4f30 -#define R300_ZB_ZMASK_PITCH 0x4f34 -#define R300_ZB_ZMASK_WRINDEX 0x4f38 -#define R300_ZB_ZMASK_DWORD 0x4f3c -#define R300_ZB_ZMASK_RDINDEX 0x4f40 - -/* Hierarchical Z Memory Offset */ -#define R300_ZB_HIZ_OFFSET 0x4f44 - -/* Hierarchical Z Write Index */ -#define R300_ZB_HIZ_WRINDEX 0x4f48 - -/* Hierarchical Z Data */ -#define R300_ZB_HIZ_DWORD 0x4f4c - -/* Hierarchical Z Read Index */ -#define R300_ZB_HIZ_RDINDEX 0x4f50 - -/* Hierarchical Z Pitch */ -#define R300_ZB_HIZ_PITCH 0x4f54 - -/* Z Buffer Z Pass Counter Data */ -#define R300_ZB_ZPASS_DATA 0x4f58 - -/* Z Buffer Z Pass Counter Address */ -#define R300_ZB_ZPASS_ADDR 0x4f5c - -/* Depth buffer X and Y coordinate offset */ -#define R300_ZB_DEPTHXY_OFFSET 0x4f60 -# define R300_DEPTHX_OFFSET_SHIFT 1 -# define R300_DEPTHX_OFFSET_MASK 0x000007FE -# define R300_DEPTHY_OFFSET_SHIFT 17 -# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 - -/* Sets the fifo sizes */ -#define R500_ZB_FIFO_SIZE 0x4fd0 -# define R500_OP_FIFO_SIZE_FULL (0 << 0) -# define R500_OP_FIFO_SIZE_HALF (1 << 0) -# define R500_OP_FIFO_SIZE_QUATER (2 << 0) -# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) - -/* Stencil Reference Value and Mask for backfacing quads */ -/* R300_ZB_STENCILREFMASK handles front face */ -#define R500_ZB_STENCILREFMASK_BF 0x4fd4 -# define R500_STENCILREF_SHIFT 0 -# define R500_STENCILREF_MASK 0x000000ff -# define R500_STENCILMASK_SHIFT 8 -# define R500_STENCILMASK_MASK 0x0000ff00 -# define R500_STENCILWRITEMASK_SHIFT 16 -# define R500_STENCILWRITEMASK_MASK 0x00ff0000 - -/** - * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION - * - * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector - * Engine instruction or a Math Engine instruction. - */ - -/*\{*/ - -enum { - /* R3XX */ - VECTOR_NO_OP = 0, - VE_DOT_PRODUCT = 1, - VE_MULTIPLY = 2, - VE_ADD = 3, - VE_MULTIPLY_ADD = 4, - VE_DISTANCE_VECTOR = 5, - VE_FRACTION = 6, - VE_MAXIMUM = 7, - VE_MINIMUM = 8, - VE_SET_GREATER_THAN_EQUAL = 9, - VE_SET_LESS_THAN = 10, - VE_MULTIPLYX2_ADD = 11, - VE_MULTIPLY_CLAMP = 12, - VE_FLT2FIX_DX = 13, - VE_FLT2FIX_DX_RND = 14, - /* R5XX */ - VE_PRED_SET_EQ_PUSH = 15, - VE_PRED_SET_GT_PUSH = 16, - VE_PRED_SET_GTE_PUSH = 17, - VE_PRED_SET_NEQ_PUSH = 18, - VE_COND_WRITE_EQ = 19, - VE_COND_WRITE_GT = 20, - VE_COND_WRITE_GTE = 21, - VE_COND_WRITE_NEQ = 22, - VE_COND_MUX_EQ = 23, - VE_COND_MUX_GT = 24, - VE_COND_MUX_GTE = 25, - VE_SET_GREATER_THAN = 26, - VE_SET_EQUAL = 27, - VE_SET_NOT_EQUAL = 28, -}; - -enum { - /* R3XX */ - MATH_NO_OP = 0, - ME_EXP_BASE2_DX = 1, - ME_LOG_BASE2_DX = 2, - ME_EXP_BASEE_FF = 3, - ME_LIGHT_COEFF_DX = 4, - ME_POWER_FUNC_FF = 5, - ME_RECIP_DX = 6, - ME_RECIP_FF = 7, - ME_RECIP_SQRT_DX = 8, - ME_RECIP_SQRT_FF = 9, - ME_MULTIPLY = 10, - ME_EXP_BASE2_FULL_DX = 11, - ME_LOG_BASE2_FULL_DX = 12, - ME_POWER_FUNC_FF_CLAMP_B = 13, - ME_POWER_FUNC_FF_CLAMP_B1 = 14, - ME_POWER_FUNC_FF_CLAMP_01 = 15, - ME_SIN = 16, - ME_COS = 17, - /* R5XX */ - ME_LOG_BASE2_IEEE = 18, - ME_RECIP_IEEE = 19, - ME_RECIP_SQRT_IEEE = 20, - ME_PRED_SET_EQ = 21, - ME_PRED_SET_GT = 22, - ME_PRED_SET_GTE = 23, - ME_PRED_SET_NEQ = 24, - ME_PRED_SET_CLR = 25, - ME_PRED_SET_INV = 26, - ME_PRED_SET_POP = 27, - ME_PRED_SET_RESTORE = 28, -}; - -enum { - /* R3XX */ - PVS_MACRO_OP_2CLK_MADD = 0, - PVS_MACRO_OP_2CLK_M2X_ADD = 1, -}; - -enum { - PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */ - PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */ - PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */ - PVS_SRC_REG_ALT_TEMPORARY = 3, /* Alternate Intermediate Storage */ -}; - -enum { - PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */ - PVS_DST_REG_A0 = 1, /* Address Register Storage */ - PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */ - PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */ - PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */ - PVS_DST_REG_INPUT = 5, /* Output Memory & Replicate X to all channels */ -}; - -enum { - PVS_SRC_SELECT_X = 0, /* Select X Component */ - PVS_SRC_SELECT_Y = 1, /* Select Y Component */ - PVS_SRC_SELECT_Z = 2, /* Select Z Component */ - PVS_SRC_SELECT_W = 3, /* Select W Component */ - PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */ - PVS_SRC_SELECT_FORCE_1 = 5, /* Force Component to 1.0 */ -}; - -/* PVS Opcode & Destination Operand Description */ - -enum { - PVS_DST_OPCODE_MASK = 0x3f, - PVS_DST_OPCODE_SHIFT = 0, - PVS_DST_MATH_INST_MASK = 0x1, - PVS_DST_MATH_INST_SHIFT = 6, - PVS_DST_MACRO_INST_MASK = 0x1, - PVS_DST_MACRO_INST_SHIFT = 7, - PVS_DST_REG_TYPE_MASK = 0xf, - PVS_DST_REG_TYPE_SHIFT = 8, - PVS_DST_ADDR_MODE_1_MASK = 0x1, - PVS_DST_ADDR_MODE_1_SHIFT = 12, - PVS_DST_OFFSET_MASK = 0x7f, - PVS_DST_OFFSET_SHIFT = 13, - PVS_DST_WE_X_MASK = 0x1, - PVS_DST_WE_X_SHIFT = 20, - PVS_DST_WE_Y_MASK = 0x1, - PVS_DST_WE_Y_SHIFT = 21, - PVS_DST_WE_Z_MASK = 0x1, - PVS_DST_WE_Z_SHIFT = 22, - PVS_DST_WE_W_MASK = 0x1, - PVS_DST_WE_W_SHIFT = 23, - PVS_DST_VE_SAT_MASK = 0x1, - PVS_DST_VE_SAT_SHIFT = 24, - PVS_DST_ME_SAT_MASK = 0x1, - PVS_DST_ME_SAT_SHIFT = 25, - PVS_DST_PRED_ENABLE_MASK = 0x1, - PVS_DST_PRED_ENABLE_SHIFT = 26, - PVS_DST_PRED_SENSE_MASK = 0x1, - PVS_DST_PRED_SENSE_SHIFT = 27, - PVS_DST_DUAL_MATH_OP_MASK = 0x3, - PVS_DST_DUAL_MATH_OP_SHIFT = 27, - PVS_DST_ADDR_SEL_MASK = 0x3, - PVS_DST_ADDR_SEL_SHIFT = 29, - PVS_DST_ADDR_MODE_0_MASK = 0x1, - PVS_DST_ADDR_MODE_0_SHIFT = 31, -}; - -/* PVS Source Operand Description */ - -enum { - PVS_SRC_REG_TYPE_MASK = 0x3, - PVS_SRC_REG_TYPE_SHIFT = 0, - SPARE_0_MASK = 0x1, - SPARE_0_SHIFT = 2, - PVS_SRC_ABS_XYZW_MASK = 0x1, - PVS_SRC_ABS_XYZW_SHIFT = 3, - PVS_SRC_ADDR_MODE_0_MASK = 0x1, - PVS_SRC_ADDR_MODE_0_SHIFT = 4, - PVS_SRC_OFFSET_MASK = 0xff, - PVS_SRC_OFFSET_SHIFT = 5, - PVS_SRC_SWIZZLE_X_MASK = 0x7, - PVS_SRC_SWIZZLE_X_SHIFT = 13, - PVS_SRC_SWIZZLE_Y_MASK = 0x7, - PVS_SRC_SWIZZLE_Y_SHIFT = 16, - PVS_SRC_SWIZZLE_Z_MASK = 0x7, - PVS_SRC_SWIZZLE_Z_SHIFT = 19, - PVS_SRC_SWIZZLE_W_MASK = 0x7, - PVS_SRC_SWIZZLE_W_SHIFT = 22, - PVS_SRC_MODIFIER_X_MASK = 0x1, - PVS_SRC_MODIFIER_X_SHIFT = 25, - PVS_SRC_MODIFIER_Y_MASK = 0x1, - PVS_SRC_MODIFIER_Y_SHIFT = 26, - PVS_SRC_MODIFIER_Z_MASK = 0x1, - PVS_SRC_MODIFIER_Z_SHIFT = 27, - PVS_SRC_MODIFIER_W_MASK = 0x1, - PVS_SRC_MODIFIER_W_SHIFT = 28, - PVS_SRC_ADDR_SEL_MASK = 0x3, - PVS_SRC_ADDR_SEL_SHIFT = 29, - PVS_SRC_ADDR_MODE_1_MASK = 0x0, - PVS_SRC_ADDR_MODE_1_SHIFT = 32, -}; - - -#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class) \ - (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \ - | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \ - | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \ - | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \ - | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \ - | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) - -#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \ - (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \ - | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \ - | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \ - | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \ - | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \ - | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \ - | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT)) - -/*\}*/ - -/* BEGIN: Packet 3 commands */ - -/* A primitive emission dword. */ -#define R300_PRIM_TYPE_NONE (0 << 0) -#define R300_PRIM_TYPE_POINT (1 << 0) -#define R300_PRIM_TYPE_LINE (2 << 0) -#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) -#define R300_PRIM_TYPE_TRI_LIST (4 << 0) -#define R300_PRIM_TYPE_TRI_FAN (5 << 0) -#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) -#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) -#define R300_PRIM_TYPE_RECT_LIST (8 << 0) -#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) -#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) - /* GUESS (based on r200) */ -#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) -#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) -#define R300_PRIM_TYPE_QUADS (13 << 0) -#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) -#define R300_PRIM_TYPE_POLYGON (15 << 0) -#define R300_PRIM_TYPE_MASK 0xF -#define R300_PRIM_WALK_IND (1 << 4) -#define R300_PRIM_WALK_LIST (2 << 4) -#define R300_PRIM_WALK_RING (3 << 4) -#define R300_PRIM_WALK_MASK (3 << 4) - /* GUESS (based on r200) */ -#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) -#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) -#define R300_PRIM_NUM_VERTICES_SHIFT 16 -#define R300_PRIM_NUM_VERTICES_MASK 0xffff - - - -/* - * The R500 unified shader (US) registers come in banks of 512 each, one - * for each instruction slot in the shader. You can't touch them directly. - * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive - * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the - * instruction is fully specified. - */ -#define R500_US_ALU_ALPHA_INST_0 0xa800 -# define R500_ALPHA_OP_MAD 0 -# define R500_ALPHA_OP_DP 1 -# define R500_ALPHA_OP_MIN 2 -# define R500_ALPHA_OP_MAX 3 -/* #define R500_ALPHA_OP_RESERVED 4 */ -# define R500_ALPHA_OP_CND 5 -# define R500_ALPHA_OP_CMP 6 -# define R500_ALPHA_OP_FRC 7 -# define R500_ALPHA_OP_EX2 8 -# define R500_ALPHA_OP_LN2 9 -# define R500_ALPHA_OP_RCP 10 -# define R500_ALPHA_OP_RSQ 11 -# define R500_ALPHA_OP_SIN 12 -# define R500_ALPHA_OP_COS 13 -# define R500_ALPHA_OP_MDH 14 -# define R500_ALPHA_OP_MDV 15 -# define R500_ALPHA_ADDRD(x) ((x) << 4) -# define R500_ALPHA_ADDRD_REL (1 << 11) -# define R500_ALPHA_SEL_A_SHIFT 12 -# define R500_ALPHA_SEL_A_SRC0 (0 << 12) -# define R500_ALPHA_SEL_A_SRC1 (1 << 12) -# define R500_ALPHA_SEL_A_SRC2 (2 << 12) -# define R500_ALPHA_SEL_A_SRCP (3 << 12) -# define R500_ALPHA_SWIZ_A_R (0 << 14) -# define R500_ALPHA_SWIZ_A_G (1 << 14) -# define R500_ALPHA_SWIZ_A_B (2 << 14) -# define R500_ALPHA_SWIZ_A_A (3 << 14) -# define R500_ALPHA_SWIZ_A_0 (4 << 14) -# define R500_ALPHA_SWIZ_A_HALF (5 << 14) -# define R500_ALPHA_SWIZ_A_1 (6 << 14) -/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ -# define R500_ALPHA_MOD_A_NOP (0 << 17) -# define R500_ALPHA_MOD_A_NEG (1 << 17) -# define R500_ALPHA_MOD_A_ABS (2 << 17) -# define R500_ALPHA_MOD_A_NAB (3 << 17) -# define R500_ALPHA_SEL_B_SHIFT 19 -# define R500_ALPHA_SEL_B_SRC0 (0 << 19) -# define R500_ALPHA_SEL_B_SRC1 (1 << 19) -# define R500_ALPHA_SEL_B_SRC2 (2 << 19) -# define R500_ALPHA_SEL_B_SRCP (3 << 19) -# define R500_ALPHA_SWIZ_B_R (0 << 21) -# define R500_ALPHA_SWIZ_B_G (1 << 21) -# define R500_ALPHA_SWIZ_B_B (2 << 21) -# define R500_ALPHA_SWIZ_B_A (3 << 21) -# define R500_ALPHA_SWIZ_B_0 (4 << 21) -# define R500_ALPHA_SWIZ_B_HALF (5 << 21) -# define R500_ALPHA_SWIZ_B_1 (6 << 21) -/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ -# define R500_ALPHA_MOD_B_NOP (0 << 24) -# define R500_ALPHA_MOD_B_NEG (1 << 24) -# define R500_ALPHA_MOD_B_ABS (2 << 24) -# define R500_ALPHA_MOD_B_NAB (3 << 24) -# define R500_ALPHA_OMOD_IDENTITY (0 << 26) -# define R500_ALPHA_OMOD_MUL_2 (1 << 26) -# define R500_ALPHA_OMOD_MUL_4 (2 << 26) -# define R500_ALPHA_OMOD_MUL_8 (3 << 26) -# define R500_ALPHA_OMOD_DIV_2 (4 << 26) -# define R500_ALPHA_OMOD_DIV_4 (5 << 26) -# define R500_ALPHA_OMOD_DIV_8 (6 << 26) -# define R500_ALPHA_OMOD_DISABLE (7 << 26) -# define R500_ALPHA_TARGET(x) ((x) << 29) -# define R500_ALPHA_W_OMASK (1 << 31) -#define R500_US_ALU_ALPHA_ADDR_0 0x9800 -# define R500_ALPHA_ADDR0(x) ((x) << 0) -# define R500_ALPHA_ADDR0_CONST (1 << 8) -# define R500_ALPHA_ADDR0_REL (1 << 9) -# define R500_ALPHA_ADDR1(x) ((x) << 10) -# define R500_ALPHA_ADDR1_CONST (1 << 18) -# define R500_ALPHA_ADDR1_REL (1 << 19) -# define R500_ALPHA_ADDR2(x) ((x) << 20) -# define R500_ALPHA_ADDR2_CONST (1 << 28) -# define R500_ALPHA_ADDR2_REL (1 << 29) -# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) -# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) -# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) -# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) -#define R500_US_ALU_RGBA_INST_0 0xb000 -# define R500_ALU_RGBA_OP_MAD (0 << 0) -# define R500_ALU_RGBA_OP_DP3 (1 << 0) -# define R500_ALU_RGBA_OP_DP4 (2 << 0) -# define R500_ALU_RGBA_OP_D2A (3 << 0) -# define R500_ALU_RGBA_OP_MIN (4 << 0) -# define R500_ALU_RGBA_OP_MAX (5 << 0) -/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ -# define R500_ALU_RGBA_OP_CND (7 << 0) -# define R500_ALU_RGBA_OP_CMP (8 << 0) -# define R500_ALU_RGBA_OP_FRC (9 << 0) -# define R500_ALU_RGBA_OP_SOP (10 << 0) -# define R500_ALU_RGBA_OP_MDH (11 << 0) -# define R500_ALU_RGBA_OP_MDV (12 << 0) -# define R500_ALU_RGBA_ADDRD(x) ((x) << 4) -# define R500_ALU_RGBA_ADDRD_REL (1 << 11) -# define R500_ALU_RGBA_SEL_C_SHIFT 12 -# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) -# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) -# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) -# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) -# define R500_ALU_RGBA_R_SWIZ_R (0 << 14) -# define R500_ALU_RGBA_R_SWIZ_G (1 << 14) -# define R500_ALU_RGBA_R_SWIZ_B (2 << 14) -# define R500_ALU_RGBA_R_SWIZ_A (3 << 14) -# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) -# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) -# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) -/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ -# define R500_ALU_RGBA_G_SWIZ_R (0 << 17) -# define R500_ALU_RGBA_G_SWIZ_G (1 << 17) -# define R500_ALU_RGBA_G_SWIZ_B (2 << 17) -# define R500_ALU_RGBA_G_SWIZ_A (3 << 17) -# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) -# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) -# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) -/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ -# define R500_ALU_RGBA_B_SWIZ_R (0 << 20) -# define R500_ALU_RGBA_B_SWIZ_G (1 << 20) -# define R500_ALU_RGBA_B_SWIZ_B (2 << 20) -# define R500_ALU_RGBA_B_SWIZ_A (3 << 20) -# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) -# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) -# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) -/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ -# define R500_ALU_RGBA_MOD_C_NOP (0 << 23) -# define R500_ALU_RGBA_MOD_C_NEG (1 << 23) -# define R500_ALU_RGBA_MOD_C_ABS (2 << 23) -# define R500_ALU_RGBA_MOD_C_NAB (3 << 23) -# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25 -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) -# define R500_ALU_RGBA_A_SWIZ_R (0 << 27) -# define R500_ALU_RGBA_A_SWIZ_G (1 << 27) -# define R500_ALU_RGBA_A_SWIZ_B (2 << 27) -# define R500_ALU_RGBA_A_SWIZ_A (3 << 27) -# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) -# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) -# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) -/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ -# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) -#define R500_US_ALU_RGB_INST_0 0xa000 -# define R500_ALU_RGB_SEL_A_SHIFT 0 -# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) -# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) -# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) -# define R500_ALU_RGB_SEL_A_SRCP (3 << 0) -# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) -# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) -# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) -# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) -# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) -# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) -# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) -/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ -# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) -# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) -# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) -# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) -# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) -# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) -# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) -/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ -# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) -# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) -# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) -# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) -# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) -# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) -# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) -/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ -# define R500_ALU_RGB_MOD_A_NOP (0 << 11) -# define R500_ALU_RGB_MOD_A_NEG (1 << 11) -# define R500_ALU_RGB_MOD_A_ABS (2 << 11) -# define R500_ALU_RGB_MOD_A_NAB (3 << 11) -# define R500_ALU_RGB_SEL_B_SHIFT 13 -# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) -# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) -# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) -# define R500_ALU_RGB_SEL_B_SRCP (3 << 13) -# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) -# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) -# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) -# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) -# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) -# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) -# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) -/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ -# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) -# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) -# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) -# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) -# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) -# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) -# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) -/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ -# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) -# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) -# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) -# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) -# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) -# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) -# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) -/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ -# define R500_ALU_RGB_MOD_B_NOP (0 << 24) -# define R500_ALU_RGB_MOD_B_NEG (1 << 24) -# define R500_ALU_RGB_MOD_B_ABS (2 << 24) -# define R500_ALU_RGB_MOD_B_NAB (3 << 24) -# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) -# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) -# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) -# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) -# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) -# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) -# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) -# define R500_ALU_RGB_OMOD_DISABLE (7 << 26) -# define R500_ALU_RGB_TARGET(x) ((x) << 29) -# define R500_ALU_RGB_WMASK (1 << 31) -#define R500_US_ALU_RGB_ADDR_0 0x9000 -# define R500_RGB_ADDR0(x) ((x) << 0) -# define R500_RGB_ADDR0_CONST (1 << 8) -# define R500_RGB_ADDR0_REL (1 << 9) -# define R500_RGB_ADDR1(x) ((x) << 10) -# define R500_RGB_ADDR1_CONST (1 << 18) -# define R500_RGB_ADDR1_REL (1 << 19) -# define R500_RGB_ADDR2(x) ((x) << 20) -# define R500_RGB_ADDR2_CONST (1 << 28) -# define R500_RGB_ADDR2_REL (1 << 29) -# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) -# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) -# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) -# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) -#define R500_US_CMN_INST_0 0xb800 -# define R500_INST_TYPE_MASK (3 << 0) -# define R500_INST_TYPE_ALU (0 << 0) -# define R500_INST_TYPE_OUT (1 << 0) -# define R500_INST_TYPE_FC (2 << 0) -# define R500_INST_TYPE_TEX (3 << 0) -# define R500_INST_TEX_SEM_WAIT (1 << 2) -# define R500_INST_RGB_PRED_SEL_NONE (0 << 3) -# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) -# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) -# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) -# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) -# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) -# define R500_INST_RGB_PRED_INV (1 << 6) -# define R500_INST_WRITE_INACTIVE (1 << 7) -# define R500_INST_LAST (1 << 8) -# define R500_INST_NOP (1 << 9) -# define R500_INST_ALU_WAIT (1 << 10) -# define R500_INST_RGB_WMASK_R (1 << 11) -# define R500_INST_RGB_WMASK_G (1 << 12) -# define R500_INST_RGB_WMASK_B (1 << 13) -# define R500_INST_ALPHA_WMASK (1 << 14) -# define R500_INST_RGB_OMASK_R (1 << 15) -# define R500_INST_RGB_OMASK_G (1 << 16) -# define R500_INST_RGB_OMASK_B (1 << 17) -# define R500_INST_ALPHA_OMASK (1 << 18) -# define R500_INST_RGB_CLAMP (1 << 19) -# define R500_INST_ALPHA_CLAMP (1 << 20) -# define R500_INST_ALU_RESULT_SEL (1 << 21) -# define R500_INST_ALU_RESULT_SEL_RED (0 << 21) -# define R500_INST_ALU_RESULT_SEL_ALPHA (1 << 21) -# define R500_INST_ALPHA_PRED_INV (1 << 22) -# define R500_INST_ALU_RESULT_OP_EQ (0 << 23) -# define R500_INST_ALU_RESULT_OP_LT (1 << 23) -# define R500_INST_ALU_RESULT_OP_GE (2 << 23) -# define R500_INST_ALU_RESULT_OP_NE (3 << 23) -# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) -# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) -# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) -# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) -# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) -# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) -/* XXX next four are kind of guessed */ -# define R500_INST_STAT_WE_R (1 << 28) -# define R500_INST_STAT_WE_G (1 << 29) -# define R500_INST_STAT_WE_B (1 << 30) -# define R500_INST_STAT_WE_A (1 << 31) - -/* note that these are 8 bit lengths, despite the offsets, at least for R500 */ -#define R500_US_CODE_ADDR 0x4630 -# define R500_US_CODE_START_ADDR(x) ((x) << 0) -# define R500_US_CODE_END_ADDR(x) ((x) << 16) -#define R500_US_CODE_OFFSET 0x4638 -# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0) -#define R500_US_CODE_RANGE 0x4634 -# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0) -# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16) -#define R500_US_CONFIG 0x4600 -# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) -#define R500_US_FC_ADDR_0 0xa000 -# define R500_FC_BOOL_ADDR(x) ((x) << 0) -# define R500_FC_INT_ADDR(x) ((x) << 8) -# define R500_FC_JUMP_ADDR(x) ((x) << 16) -# define R500_FC_JUMP_GLOBAL (1 << 31) -#define R500_US_FC_BOOL_CONST 0x4620 -# define R500_FC_KBOOL(x) (x) -#define R500_US_FC_CTRL 0x4624 -# define R500_FC_TEST_EN (1 << 30) -# define R500_FC_FULL_FC_EN (1 << 31) -#define R500_US_FC_INST_0 0x9800 -# define R500_FC_OP_JUMP (0 << 0) -# define R500_FC_OP_LOOP (1 << 0) -# define R500_FC_OP_ENDLOOP (2 << 0) -# define R500_FC_OP_REP (3 << 0) -# define R500_FC_OP_ENDREP (4 << 0) -# define R500_FC_OP_BREAKLOOP (5 << 0) -# define R500_FC_OP_BREAKREP (6 << 0) -# define R500_FC_OP_CONTINUE (7 << 0) -# define R500_FC_B_ELSE (1 << 4) -# define R500_FC_JUMP_ANY (1 << 5) -# define R500_FC_A_OP_NONE (0 << 6) -# define R500_FC_A_OP_POP (1 << 6) -# define R500_FC_A_OP_PUSH (2 << 6) -# define R500_FC_JUMP_FUNC(x) ((x) << 8) -# define R500_FC_B_POP_CNT(x) ((x) << 16) -# define R500_FC_B_OP0_NONE (0 << 24) -# define R500_FC_B_OP0_DECR (1 << 24) -# define R500_FC_B_OP0_INCR (2 << 24) -# define R500_FC_B_OP1_NONE (0 << 26) -# define R500_FC_B_OP1_DECR (1 << 26) -# define R500_FC_B_OP1_INCR (2 << 26) -# define R500_FC_IGNORE_UNCOVERED (1 << 28) -#define R500_US_FC_INT_CONST_0 0x4c00 -# define R500_FC_INT_CONST_KR(x) ((x) << 0) -# define R500_FC_INT_CONST_KG(x) ((x) << 8) -# define R500_FC_INT_CONST_KB(x) ((x) << 16) -/* _0 through _15 */ -#define R500_US_FORMAT0_0 0x4640 -# define R500_FORMAT_TXWIDTH(x) ((x) << 0) -# define R500_FORMAT_TXHEIGHT(x) ((x) << 11) -# define R500_FORMAT_TXDEPTH(x) ((x) << 22) -/* _0 through _3 */ -#define R500_US_OUT_FMT_0 0x46a4 -# define R500_OUT_FMT_C4_8 (0 << 0) -# define R500_OUT_FMT_C4_10 (1 << 0) -# define R500_OUT_FMT_C4_10_GAMMA (2 << 0) -# define R500_OUT_FMT_C_16 (3 << 0) -# define R500_OUT_FMT_C2_16 (4 << 0) -# define R500_OUT_FMT_C4_16 (5 << 0) -# define R500_OUT_FMT_C_16_MPEG (6 << 0) -# define R500_OUT_FMT_C2_16_MPEG (7 << 0) -# define R500_OUT_FMT_C2_4 (8 << 0) -# define R500_OUT_FMT_C_3_3_2 (9 << 0) -# define R500_OUT_FMT_C_6_5_6 (10 << 0) -# define R500_OUT_FMT_C_11_11_10 (11 << 0) -# define R500_OUT_FMT_C_10_11_11 (12 << 0) -# define R500_OUT_FMT_C_2_10_10_10 (13 << 0) -/* #define R500_OUT_FMT_RESERVED (14 << 0) */ -# define R500_OUT_FMT_UNUSED (15 << 0) -# define R500_OUT_FMT_C_16_FP (16 << 0) -# define R500_OUT_FMT_C2_16_FP (17 << 0) -# define R500_OUT_FMT_C4_16_FP (18 << 0) -# define R500_OUT_FMT_C_32_FP (19 << 0) -# define R500_OUT_FMT_C2_32_FP (20 << 0) -# define R500_OUT_FMT_C4_32_FP (21 << 0) -# define R500_C0_SEL_A (0 << 8) -# define R500_C0_SEL_R (1 << 8) -# define R500_C0_SEL_G (2 << 8) -# define R500_C0_SEL_B (3 << 8) -# define R500_C1_SEL_A (0 << 10) -# define R500_C1_SEL_R (1 << 10) -# define R500_C1_SEL_G (2 << 10) -# define R500_C1_SEL_B (3 << 10) -# define R500_C2_SEL_A (0 << 12) -# define R500_C2_SEL_R (1 << 12) -# define R500_C2_SEL_G (2 << 12) -# define R500_C2_SEL_B (3 << 12) -# define R500_C3_SEL_A (0 << 14) -# define R500_C3_SEL_R (1 << 14) -# define R500_C3_SEL_G (2 << 14) -# define R500_C3_SEL_B (3 << 14) -# define R500_OUT_SIGN(x) ((x) << 16) -# define R500_ROUND_ADJ (1 << 20) -#define R500_US_PIXSIZE 0x4604 -# define R500_PIX_SIZE(x) (x) -#define R500_US_TEX_ADDR_0 0x9800 -# define R500_TEX_SRC_ADDR(x) ((x) << 0) -# define R500_TEX_SRC_ADDR_REL (1 << 7) -# define R500_TEX_SRC_S_SWIZ_R (0 << 8) -# define R500_TEX_SRC_S_SWIZ_G (1 << 8) -# define R500_TEX_SRC_S_SWIZ_B (2 << 8) -# define R500_TEX_SRC_S_SWIZ_A (3 << 8) -# define R500_TEX_SRC_T_SWIZ_R (0 << 10) -# define R500_TEX_SRC_T_SWIZ_G (1 << 10) -# define R500_TEX_SRC_T_SWIZ_B (2 << 10) -# define R500_TEX_SRC_T_SWIZ_A (3 << 10) -# define R500_TEX_SRC_R_SWIZ_R (0 << 12) -# define R500_TEX_SRC_R_SWIZ_G (1 << 12) -# define R500_TEX_SRC_R_SWIZ_B (2 << 12) -# define R500_TEX_SRC_R_SWIZ_A (3 << 12) -# define R500_TEX_SRC_Q_SWIZ_R (0 << 14) -# define R500_TEX_SRC_Q_SWIZ_G (1 << 14) -# define R500_TEX_SRC_Q_SWIZ_B (2 << 14) -# define R500_TEX_SRC_Q_SWIZ_A (3 << 14) -# define R500_TEX_DST_ADDR(x) ((x) << 16) -# define R500_TEX_DST_ADDR_REL (1 << 23) -# define R500_TEX_DST_R_SWIZ_R (0 << 24) -# define R500_TEX_DST_R_SWIZ_G (1 << 24) -# define R500_TEX_DST_R_SWIZ_B (2 << 24) -# define R500_TEX_DST_R_SWIZ_A (3 << 24) -# define R500_TEX_DST_G_SWIZ_R (0 << 26) -# define R500_TEX_DST_G_SWIZ_G (1 << 26) -# define R500_TEX_DST_G_SWIZ_B (2 << 26) -# define R500_TEX_DST_G_SWIZ_A (3 << 26) -# define R500_TEX_DST_B_SWIZ_R (0 << 28) -# define R500_TEX_DST_B_SWIZ_G (1 << 28) -# define R500_TEX_DST_B_SWIZ_B (2 << 28) -# define R500_TEX_DST_B_SWIZ_A (3 << 28) -# define R500_TEX_DST_A_SWIZ_R (0 << 30) -# define R500_TEX_DST_A_SWIZ_G (1 << 30) -# define R500_TEX_DST_A_SWIZ_B (2 << 30) -# define R500_TEX_DST_A_SWIZ_A (3 << 30) -#define R500_US_TEX_ADDR_DXDY_0 0xa000 -# define R500_DX_ADDR(x) ((x) << 0) -# define R500_DX_ADDR_REL (1 << 7) -# define R500_DX_S_SWIZ_R (0 << 8) -# define R500_DX_S_SWIZ_G (1 << 8) -# define R500_DX_S_SWIZ_B (2 << 8) -# define R500_DX_S_SWIZ_A (3 << 8) -# define R500_DX_T_SWIZ_R (0 << 10) -# define R500_DX_T_SWIZ_G (1 << 10) -# define R500_DX_T_SWIZ_B (2 << 10) -# define R500_DX_T_SWIZ_A (3 << 10) -# define R500_DX_R_SWIZ_R (0 << 12) -# define R500_DX_R_SWIZ_G (1 << 12) -# define R500_DX_R_SWIZ_B (2 << 12) -# define R500_DX_R_SWIZ_A (3 << 12) -# define R500_DX_Q_SWIZ_R (0 << 14) -# define R500_DX_Q_SWIZ_G (1 << 14) -# define R500_DX_Q_SWIZ_B (2 << 14) -# define R500_DX_Q_SWIZ_A (3 << 14) -# define R500_DY_ADDR(x) ((x) << 16) -# define R500_DY_ADDR_REL (1 << 17) -# define R500_DY_S_SWIZ_R (0 << 24) -# define R500_DY_S_SWIZ_G (1 << 24) -# define R500_DY_S_SWIZ_B (2 << 24) -# define R500_DY_S_SWIZ_A (3 << 24) -# define R500_DY_T_SWIZ_R (0 << 26) -# define R500_DY_T_SWIZ_G (1 << 26) -# define R500_DY_T_SWIZ_B (2 << 26) -# define R500_DY_T_SWIZ_A (3 << 26) -# define R500_DY_R_SWIZ_R (0 << 28) -# define R500_DY_R_SWIZ_G (1 << 28) -# define R500_DY_R_SWIZ_B (2 << 28) -# define R500_DY_R_SWIZ_A (3 << 28) -# define R500_DY_Q_SWIZ_R (0 << 30) -# define R500_DY_Q_SWIZ_G (1 << 30) -# define R500_DY_Q_SWIZ_B (2 << 30) -# define R500_DY_Q_SWIZ_A (3 << 30) -#define R500_US_TEX_INST_0 0x9000 -# define R500_TEX_ID(x) ((x) << 16) -# define R500_TEX_INST_NOP (0 << 22) -# define R500_TEX_INST_LD (1 << 22) -# define R500_TEX_INST_TEXKILL (2 << 22) -# define R500_TEX_INST_PROJ (3 << 22) -# define R500_TEX_INST_LODBIAS (4 << 22) -# define R500_TEX_INST_LOD (5 << 22) -# define R500_TEX_INST_DXDY (6 << 22) -# define R500_TEX_SEM_ACQUIRE (1 << 25) -# define R500_TEX_IGNORE_UNCOVERED (1 << 26) -# define R500_TEX_UNSCALED (1 << 27) -#define R300_US_W_FMT 0x46b4 -# define R300_W_FMT_W0 (0 << 0) -# define R300_W_FMT_W24 (1 << 0) -# define R300_W_FMT_W24FP (2 << 0) -# define R300_W_SRC_US (0 << 2) -# define R300_W_SRC_RAS (1 << 2) - - -/* Packet0 field ordering to write all values to the same reg */ -#define RADEON_ONE_REG_WR (1 << 15) - -/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. - * Two parameter dwords: - * 0. VAP_VTX_FMT: The first parameter is not written to hardware - * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. - */ -#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 - -/* Draw a primitive from immediate vertices in this packet - * Up to 16382 dwords: - * 0. VAP_VTX_FMT: The first parameter is not written to hardware - * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. - * 2 to end: Up to 16380 dwords of vertex data. - */ -#define R300_PACKET3_3D_DRAW_IMMD 0x00002900 - -/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and - * immediate vertices in this packet - * Up to 16382 dwords: - * 0. VAP_VTX_FMT: The first parameter is not written to hardware - * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. - * 2 to end: Up to 16380 dwords of vertex data. - */ -#define R300_PACKET3_3D_DRAW_INDX 0x00002A00 - - -/* Specify the full set of vertex arrays as (address, stride). - * The first parameter is the number of vertex arrays specified. - * The rest of the command is a variable length list of blocks, where - * each block is three dwords long and specifies two arrays. - * The first dword of a block is split into two words, the lower significant - * word refers to the first array, the more significant word to the second - * array in the block. - * The low byte of each word contains the size of an array entry in dwords, - * the high byte contains the stride of the array. - * The second dword of a block contains the pointer to the first array, - * the third dword of a block contains the pointer to the second array. - * Note that if the total number of arrays is odd, the third dword of - * the last block is omitted. - */ -#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 - -#define R300_PACKET3_INDX_BUFFER 0x00003300 -# define R300_INDX_BUFFER_DST_SHIFT 0 -# define R300_INDX_BUFFER_SKIP_SHIFT 16 -# define R300_INDX_BUFFER_ONE_REG_WR (1<<31) - -/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */ -#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 -/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */ -#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500 -/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */ -#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 - -/* Clears a portion of hierachical Z RAM - * 3 dword parameters - * 0. START - * 1. COUNT: 13:0 (max is 0x3FFF) - * 2. CLEAR_VALUE: Value to write into HIZ RAM. - */ -#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700 - -/* Draws a set of primitives using vertex buffers pointed by the state data. - * At least 2 Parameters: - * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword. - * 2 to end: Data or indices (see other 3D_DRAW_* packets for details) - */ -#define R300_PACKET3_3D_DRAW_128 0x00003900 - -/* END: Packet 3 commands */ - - -/* Color formats for 2d packets - */ -#define R300_CP_COLOR_FORMAT_CI8 2 -#define R300_CP_COLOR_FORMAT_ARGB1555 3 -#define R300_CP_COLOR_FORMAT_RGB565 4 -#define R300_CP_COLOR_FORMAT_ARGB8888 6 -#define R300_CP_COLOR_FORMAT_RGB332 7 -#define R300_CP_COLOR_FORMAT_RGB8 9 -#define R300_CP_COLOR_FORMAT_ARGB4444 15 - -/* - * CP type-3 packets - */ -#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 - -#endif /* _R300_REG_H */ - -/* *INDENT-ON* */ - -/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */ diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c deleted file mode 100644 index 44090ec2894..00000000000 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ /dev/null @@ -1,505 +0,0 @@ -/************************************************************************** - -Copyright (C) 2004 Nicolai Haehnle. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \brief R300 Render (Vertex Buffer Implementation) - * - * The immediate implementation has been removed from CVS in favor of the vertex - * buffer implementation. - * - * The render functions are called by the pipeline manager to render a batch of - * primitives. They return TRUE to pass on to the next stage (i.e. software - * rasterization) or FALSE to indicate that the pipeline has finished after - * rendering something. - * - * When falling back to software TCL still attempt to use hardware - * rasterization. - * - * I am not sure that the cache related registers are setup correctly, but - * obviously this does work... Further investigation is needed. - * - * \author Nicolai Haehnle <[email protected]> - * - * \todo Add immediate implementation back? Perhaps this is useful if there are - * no bugs... - */ - -#include "r300_render.h" - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/enums.h" -#include "main/macros.h" -#include "main/context.h" -#include "main/dd.h" -#include "main/simple_list.h" -#include "main/api_arrayelt.h" -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "vbo/vbo.h" -#include "vbo/vbo_split.h" -#include "r300_context.h" -#include "r300_state.h" -#include "r300_reg.h" -#include "r300_emit.h" -#include "r300_swtcl.h" - -/** - * \brief Convert a OpenGL primitive type into a R300 primitive type. - */ -int r300PrimitiveType(r300ContextPtr rmesa, int prim) -{ - switch (prim & PRIM_MODE_MASK) { - case GL_POINTS: - return R300_VAP_VF_CNTL__PRIM_POINTS; - break; - case GL_LINES: - return R300_VAP_VF_CNTL__PRIM_LINES; - break; - case GL_LINE_STRIP: - return R300_VAP_VF_CNTL__PRIM_LINE_STRIP; - break; - case GL_LINE_LOOP: - return R300_VAP_VF_CNTL__PRIM_LINE_LOOP; - break; - case GL_TRIANGLES: - return R300_VAP_VF_CNTL__PRIM_TRIANGLES; - break; - case GL_TRIANGLE_STRIP: - return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP; - break; - case GL_TRIANGLE_FAN: - return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN; - break; - case GL_QUADS: - return R300_VAP_VF_CNTL__PRIM_QUADS; - break; - case GL_QUAD_STRIP: - return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP; - break; - case GL_POLYGON: - return R300_VAP_VF_CNTL__PRIM_POLYGON; - break; - default: - assert(0); - return -1; - break; - } -} - -int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim) -{ - int verts_off = 0; - - switch (prim & PRIM_MODE_MASK) { - case GL_POINTS: - verts_off = 0; - break; - case GL_LINES: - verts_off = num_verts % 2; - break; - case GL_LINE_STRIP: - if (num_verts < 2) - verts_off = num_verts; - break; - case GL_LINE_LOOP: - if (num_verts < 2) - verts_off = num_verts; - break; - case GL_TRIANGLES: - verts_off = num_verts % 3; - break; - case GL_TRIANGLE_STRIP: - if (num_verts < 3) - verts_off = num_verts; - break; - case GL_TRIANGLE_FAN: - if (num_verts < 3) - verts_off = num_verts; - break; - case GL_QUADS: - verts_off = num_verts % 4; - break; - case GL_QUAD_STRIP: - if (num_verts < 4) - verts_off = num_verts; - else - verts_off = num_verts % 2; - break; - case GL_POLYGON: - if (num_verts < 3) - verts_off = num_verts; - break; - default: - assert(0); - return -1; - break; - } - - return num_verts - verts_off; -} - -static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type, int offset) -{ - BATCH_LOCALS(&rmesa->radeon); - int size; - - /* offset is in indices */ - BEGIN_BATCH(10); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); - if (rmesa->ind_buf.is_32bit) { - /* convert to bytes */ - offset *= 4; - size = vertex_count; - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - (vertex_count << 16) | type | - R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - } else { - /* convert to bytes */ - offset *= 2; - size = (vertex_count + 1) >> 1; - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - (vertex_count << 16) | type); - } - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | - (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH_RELOC(0, rmesa->ind_buf.bo, rmesa->ind_buf.bo_offset + offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(size); - } else { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | - (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH(rmesa->ind_buf.bo_offset + offset); - OUT_BATCH(size); - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->ind_buf.bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - } - END_BATCH(); -} - -static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) -{ - BATCH_LOCALS(&rmesa->radeon); - uint32_t voffset; - int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; - int i; - - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, - offset); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH(sz+2+(nr * 2)); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); - OUT_BATCH(nr); - - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | - (rmesa->radeon.tcl.aos[i].stride << 8) | - (rmesa->radeon.tcl.aos[i + 1].components << 16) | - (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - - voffset = rmesa->radeon.tcl.aos[i + 0].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; - OUT_BATCH_RELOC(voffset, - rmesa->radeon.tcl.aos[i].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->radeon.tcl.aos[i + 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->radeon.tcl.aos[i+1].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - - if (nr & 1) { - OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | - (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->radeon.tcl.aos[nr - 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; - OUT_BATCH_RELOC(voffset, - rmesa->radeon.tcl.aos[nr - 1].bo, - voffset, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - END_BATCH(); - } else { - - BEGIN_BATCH(sz+2+(nr * 2)); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); - OUT_BATCH(nr); - - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | - (rmesa->radeon.tcl.aos[i].stride << 8) | - (rmesa->radeon.tcl.aos[i + 1].components << 16) | - (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - - voffset = rmesa->radeon.tcl.aos[i + 0].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; - OUT_BATCH(voffset); - voffset = rmesa->radeon.tcl.aos[i + 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; - OUT_BATCH(voffset); - } - - if (nr & 1) { - OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | - (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->radeon.tcl.aos[nr - 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; - OUT_BATCH(voffset); - } - for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->radeon.tcl.aos[i + 0].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[i+0].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->radeon.tcl.aos[i + 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[i+1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - if (nr & 1) { - voffset = rmesa->radeon.tcl.aos[nr - 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[nr-1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - END_BATCH(); - } - -} - -static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) -{ - BATCH_LOCALS(&rmesa->radeon); - - r300_emit_scissor(rmesa->radeon.glCtx); - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); - END_BATCH(); -} - -void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - BATCH_LOCALS(&rmesa->radeon); - int type, num_verts; - - type = r300PrimitiveType(rmesa, prim); - num_verts = r300NumVerts(rmesa, end - start, prim); - - if (type < 0 || num_verts <= 0) - return; - - if (rmesa->ind_buf.bo) { - GLuint first, incr, offset = 0; - - if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) && - num_verts > 65500) { - WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim); - return; - } - - - r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, 0); - if (rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1); - OUT_BATCH(rmesa->radeon.tcl.aos[0].count); - END_BATCH(); - } - - r300_emit_scissor(rmesa->radeon.glCtx); - while (num_verts > 0) { - int nr; - int align; - - nr = MIN2(num_verts, 65535); - nr -= (nr - first) % incr; - - /* get alignment for IB correct */ - if (nr != num_verts) { - do { - align = nr * (rmesa->ind_buf.is_32bit ? 4 : 2); - if (align % 4) - nr -= incr; - } while(align % 4); - if (nr <= 0) { - WARN_ONCE("did the impossible happen? we never aligned nr to dword\n"); - return; - } - - } - r300FireEB(rmesa, nr, type, offset); - - num_verts -= nr; - offset += nr; - } - - } else { - GLuint first, incr, offset = 0; - - if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) && - num_verts > 65535) { - WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim); - return; - } - - if (rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1); - OUT_BATCH(rmesa->radeon.tcl.aos[0].count); - END_BATCH(); - } - - r300_emit_scissor(rmesa->radeon.glCtx); - while (num_verts > 0) { - int nr; - nr = MIN2(num_verts, 65535); - nr -= (nr - first) % incr; - r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start + offset); - r300FireAOS(rmesa, nr, type); - num_verts -= nr; - offset += nr; - } - } - COMMIT_BATCH(); -} - -static const char *getFallbackString(r300ContextPtr rmesa, uint32_t bit) -{ - static char common_fallback_str[32]; - switch (bit) { - case R300_FALLBACK_VERTEX_PROGRAM : - return "vertex program"; - case R300_FALLBACK_LINE_SMOOTH: - return "smooth lines"; - case R300_FALLBACK_POINT_SMOOTH: - return "smooth points"; - case R300_FALLBACK_POLYGON_SMOOTH: - return "smooth polygons"; - case R300_FALLBACK_LINE_STIPPLE: - return "line stipple"; - case R300_FALLBACK_POLYGON_STIPPLE: - return "polygon stipple"; - case R300_FALLBACK_STENCIL_TWOSIDE: - return "two-sided stencil"; - case R300_FALLBACK_RENDER_MODE: - return "render mode != GL_RENDER"; - case R300_FALLBACK_FRAGMENT_PROGRAM: - return "fragment program"; - case R300_FALLBACK_RADEON_COMMON: - snprintf(common_fallback_str, 32, "radeon common 0x%08x", rmesa->radeon.Fallback); - return common_fallback_str; - case R300_FALLBACK_AOS_LIMIT: - return "aos limit"; - case R300_FALLBACK_INVALID_BUFFERS: - return "invalid buffers"; - default: - return "unknown"; - } -} - -void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); - uint32_t old_fallback = rmesa->fallback; - static uint32_t fallback_warn = 0; - - if (mode) { - if ((fallback_warn & bit) == 0) { - if (RADEON_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "WARNING! Falling back to software for %s\n", getFallbackString(rmesa, bit)); - fallback_warn |= bit; - } - rmesa->fallback |= bit; - - /* update only if we change from no tcl fallbacks to some tcl fallbacks */ - if (rmesa->options.hw_tcl_enabled) { - if (((old_fallback & R300_TCL_FALLBACK_MASK) == 0) && - ((bit & R300_TCL_FALLBACK_MASK) > 0)) { - R300_STATECHANGE(rmesa, vap_cntl_status); - rmesa->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS; - } - } - - /* update only if we change from no raster fallbacks to some raster fallbacks */ - if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) && - ((bit & R300_RASTER_FALLBACK_MASK) > 0)) { - - radeon_firevertices(&rmesa->radeon); - rmesa->radeon.swtcl.RenderIndex = ~0; - _swsetup_Wakeup( ctx ); - } - } else { - rmesa->fallback &= ~bit; - - /* update only if we have disabled all tcl fallbacks */ - if (rmesa->options.hw_tcl_enabled) { - if ((old_fallback & R300_TCL_FALLBACK_MASK) == bit) { - R300_STATECHANGE(rmesa, vap_cntl_status); - rmesa->hw.vap_cntl_status.cmd[1] &= ~R300_VAP_TCL_BYPASS; - } - } - - /* update only if we have disabled all raster fallbacks */ - if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) { - _swrast_flush( ctx ); - - tnl->Driver.Render.Start = r300RenderStart; - tnl->Driver.Render.Finish = r300RenderFinish; - tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - _tnl_invalidate_vertex_state( ctx, ~0 ); - _tnl_invalidate_vertices( ctx, ~0 ); - } - } - -} diff --git a/src/mesa/drivers/dri/r300/r300_render.h b/src/mesa/drivers/dri/r300/r300_render.h deleted file mode 100644 index 5a78592c751..00000000000 --- a/src/mesa/drivers/dri/r300/r300_render.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __R300_RENDER_H__ -#define __R300_RENDER_H__ - -#include "main/mtypes.h" - -#define R300_FALLBACK_VERTEX_PROGRAM (1 << 0) -#define R300_TCL_FALLBACK_MASK 0x0000ffff - -#define R300_FALLBACK_LINE_SMOOTH (1 << 16) -#define R300_FALLBACK_POINT_SMOOTH (1 << 17) -#define R300_FALLBACK_POLYGON_SMOOTH (1 << 18) -#define R300_FALLBACK_LINE_STIPPLE (1 << 19) -#define R300_FALLBACK_POLYGON_STIPPLE (1 << 20) -#define R300_FALLBACK_STENCIL_TWOSIDE (1 << 21) -#define R300_FALLBACK_RENDER_MODE (1 << 22) -#define R300_FALLBACK_FRAGMENT_PROGRAM (1 << 23) -#define R300_FALLBACK_RADEON_COMMON (1 << 29) -#define R300_FALLBACK_AOS_LIMIT (1 << 30) -#define R300_FALLBACK_INVALID_BUFFERS (1 << 31) -#define R300_RASTER_FALLBACK_MASK 0xffff0000 - -#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -#define MASK_X R300_WRITE_ENA_X -#define MASK_Y R300_WRITE_ENA_Y -#define MASK_Z R300_WRITE_ENA_Z -#define MASK_W R300_WRITE_ENA_W - -#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \ - SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \ - SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \ - SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \ - SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \ - SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE -#error Cannot change these! -#endif - -extern const struct tnl_pipeline_stage _r300_render_stage; - -extern void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode); - -extern void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim); - -#endif diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c deleted file mode 100644 index f2bbac5b857..00000000000 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2009 Maciej Cencora <[email protected]> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "main/glheader.h" - -#include "program/program.h" -#include "tnl/tnl.h" -#include "r300_context.h" -#include "r300_fragprog_common.h" - -static void freeFragProgCache(struct gl_context *ctx, struct r300_fragment_program_cont *cache) -{ - struct r300_fragment_program *tmp, *fp = cache->progs; - - while (fp) { - tmp = fp->next; - rc_constants_destroy(&fp->code.constants); - free(fp); - fp = tmp; - } -} - -static void freeVertProgCache(struct gl_context *ctx, struct r300_vertex_program_cont *cache) -{ - struct r300_vertex_program *tmp, *vp = cache->progs; - - while (vp) { - tmp = vp->next; - rc_constants_destroy(&vp->code.constants); - _mesa_reference_vertprog(ctx, &vp->Base, NULL); - free(vp); - vp = tmp; - } -} - -static struct gl_program *r300NewProgram(struct gl_context * ctx, GLenum target, - GLuint id) -{ - struct r300_vertex_program_cont *vp; - struct r300_fragment_program_cont *fp; - - switch (target) { - case GL_VERTEX_STATE_PROGRAM_NV: - case GL_VERTEX_PROGRAM_ARB: - vp = CALLOC_STRUCT(r300_vertex_program_cont); - return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id); - - case GL_FRAGMENT_PROGRAM_NV: - case GL_FRAGMENT_PROGRAM_ARB: - fp = CALLOC_STRUCT(r300_fragment_program_cont); - return _mesa_init_fragment_program(ctx, &fp->Base, target, id); - - default: - _mesa_problem(ctx, "Bad target in r300NewProgram"); - } - - return NULL; -} - -static void r300DeleteProgram(struct gl_context * ctx, struct gl_program *prog) -{ - struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog; - struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog; - - switch (prog->Target) { - case GL_VERTEX_PROGRAM_ARB: - freeVertProgCache(ctx, vp); - break; - case GL_FRAGMENT_PROGRAM_ARB: - freeFragProgCache(ctx, fp); - break; - } - - _mesa_delete_program(ctx, prog); -} - -static GLboolean -r300ProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog) -{ - struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog; - struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog; - - switch (target) { - case GL_VERTEX_PROGRAM_ARB: - freeVertProgCache(ctx, vp); - vp->progs = NULL; - break; - case GL_FRAGMENT_PROGRAM_ARB: - freeFragProgCache(ctx, fp); - fp->progs = NULL; - break; - } - - /* need this for tcl fallbacks */ - (void) _tnl_program_string(ctx, target, prog); - - /* XXX check if program is legal, within limits */ - return GL_TRUE; -} - -static GLboolean -r300IsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog) -{ - if (target == GL_FRAGMENT_PROGRAM_ARB) { - struct r300_fragment_program *fp = r300SelectAndTranslateFragmentShader(ctx); - - return !fp->error; - } else { - struct r300_vertex_program *vp = r300SelectAndTranslateVertexShader(ctx); - - return !vp->error; - } -} - -void r300InitShaderFuncs(struct dd_function_table *functions) -{ - functions->NewProgram = r300NewProgram; - functions->DeleteProgram = r300DeleteProgram; - functions->ProgramStringNotify = r300ProgramStringNotify; - functions->IsProgramNative = r300IsProgramNative; -} diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c deleted file mode 100644 index 2f7b7ab8534..00000000000 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ /dev/null @@ -1,2416 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. -Copyright (C) 2004 Nicolai Haehnle. -All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Nicolai Haehnle <[email protected]> - */ - -#include "main/glheader.h" -#include "main/state.h" -#include "main/imports.h" -#include "main/enums.h" -#include "main/macros.h" -#include "main/context.h" -#include "main/dd.h" -#include "main/framebuffer.h" -#include "main/simple_list.h" -#include "main/api_arrayelt.h" - -#include "drivers/common/meta.h" -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "program/prog_parameter.h" -#include "program/prog_statevars.h" -#include "vbo/vbo.h" -#include "tnl/tnl.h" - -#include "r300_context.h" -#include "r300_state.h" -#include "r300_reg.h" -#include "r300_emit.h" -#include "r300_fragprog_common.h" -#include "r300_render.h" -#include "r300_vertprog.h" - -static void r300BlendColor(struct gl_context * ctx, const GLfloat cf[4]) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - - R300_STATECHANGE(rmesa, blend_color); - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - GLuint r = IROUND(cf[0]*1023.0f); - GLuint g = IROUND(cf[1]*1023.0f); - GLuint b = IROUND(cf[2]*1023.0f); - GLuint a = IROUND(cf[3]*1023.0f); - - rmesa->hw.blend_color.cmd[1] = r | (a << 16); - rmesa->hw.blend_color.cmd[2] = b | (g << 16); - } else { - GLubyte color[4]; - CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); - CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); - CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); - CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - - rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0], - color[1], color[2]); - } -} - -/** - * Calculate the hardware blend factor setting. This same function is used - * for source and destination of both alpha and RGB. - * - * \returns - * The hardware register value for the specified blend factor. This value - * will need to be shifted into the correct position for either source or - * destination factor. - * - * \todo - * Since the two cases where source and destination are handled differently - * are essentially error cases, they should never happen. Determine if these - * cases can be removed. - */ -static int blend_factor(GLenum factor, GLboolean is_src) -{ - switch (factor) { - case GL_ZERO: - return R300_BLEND_GL_ZERO; - break; - case GL_ONE: - return R300_BLEND_GL_ONE; - break; - case GL_DST_COLOR: - return R300_BLEND_GL_DST_COLOR; - break; - case GL_ONE_MINUS_DST_COLOR: - return R300_BLEND_GL_ONE_MINUS_DST_COLOR; - break; - case GL_SRC_COLOR: - return R300_BLEND_GL_SRC_COLOR; - break; - case GL_ONE_MINUS_SRC_COLOR: - return R300_BLEND_GL_ONE_MINUS_SRC_COLOR; - break; - case GL_SRC_ALPHA: - return R300_BLEND_GL_SRC_ALPHA; - break; - case GL_ONE_MINUS_SRC_ALPHA: - return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA; - break; - case GL_DST_ALPHA: - return R300_BLEND_GL_DST_ALPHA; - break; - case GL_ONE_MINUS_DST_ALPHA: - return R300_BLEND_GL_ONE_MINUS_DST_ALPHA; - break; - case GL_SRC_ALPHA_SATURATE: - return (is_src) ? R300_BLEND_GL_SRC_ALPHA_SATURATE : - R300_BLEND_GL_ZERO; - break; - case GL_CONSTANT_COLOR: - return R300_BLEND_GL_CONST_COLOR; - break; - case GL_ONE_MINUS_CONSTANT_COLOR: - return R300_BLEND_GL_ONE_MINUS_CONST_COLOR; - break; - case GL_CONSTANT_ALPHA: - return R300_BLEND_GL_CONST_ALPHA; - break; - case GL_ONE_MINUS_CONSTANT_ALPHA: - return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA; - break; - default: - fprintf(stderr, "unknown blend factor %x\n", factor); - return (is_src) ? R300_BLEND_GL_ONE : R300_BLEND_GL_ZERO; - break; - } -} - -/** - * Sets both the blend equation and the blend function. - * This is done in a single - * function because some blend equations (i.e., \c GL_MIN and \c GL_MAX) - * change the interpretation of the blend function. - * Also, make sure that blend function and blend equation are set to their - * default value if color blending is not enabled, since at least blend - * equations GL_MIN and GL_FUNC_REVERSE_SUBTRACT will cause wrong results - * otherwise for unknown reasons. - */ - -/* helper function */ -static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn, - int cbits, int funcA, int eqnA) -{ - GLuint new_ablend, new_cblend; - -#if 0 - fprintf(stderr, - "eqnA=%08x funcA=%08x eqn=%08x func=%08x cbits=%08x\n", - eqnA, funcA, eqn, func, cbits); -#endif - new_ablend = eqnA | funcA; - new_cblend = eqn | func; - - /* Some blend factor combinations don't seem to work when the - * BLEND_NO_SEPARATE bit is set. - * - * Especially problematic candidates are the ONE_MINUS_* flags, - * but I can't see a real pattern. - */ -#if 0 - if (new_ablend == new_cblend) { - new_cblend |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; - } -#endif - new_cblend |= cbits; - - if ((new_ablend != r300->hw.bld.cmd[R300_BLD_ABLEND]) || - (new_cblend != r300->hw.bld.cmd[R300_BLD_CBLEND])) { - R300_STATECHANGE(r300, bld); - r300->hw.bld.cmd[R300_BLD_ABLEND] = new_ablend; - r300->hw.bld.cmd[R300_BLD_CBLEND] = new_cblend; - } -} - -static void r300SetBlendState(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT); - int eqn = R300_COMB_FCN_ADD_CLAMP; - int funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT); - int eqnA = R300_COMB_FCN_ADD_CLAMP; - - if (ctx->Color.ColorLogicOpEnabled || !ctx->Color.BlendEnabled) { - r300SetBlendCntl(r300, func, eqn, 0, func, eqn); - return; - } - - func = - (blend_factor(ctx->Color.Blend[0].SrcRGB, GL_TRUE) << - R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.Blend[0].DstRGB, - GL_FALSE) << - R300_DST_BLEND_SHIFT); - - switch (ctx->Color.Blend[0].EquationRGB) { - case GL_FUNC_ADD: - eqn = R300_COMB_FCN_ADD_CLAMP; - break; - - case GL_FUNC_SUBTRACT: - eqn = R300_COMB_FCN_SUB_CLAMP; - break; - - case GL_FUNC_REVERSE_SUBTRACT: - eqn = R300_COMB_FCN_RSUB_CLAMP; - break; - - case GL_MIN: - eqn = R300_COMB_FCN_MIN; - func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); - break; - - case GL_MAX: - eqn = R300_COMB_FCN_MAX; - func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); - break; - - default: - fprintf(stderr, - "[%s:%u] Invalid RGB blend equation (0x%04x).\n", - __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationRGB); - return; - } - - funcA = - (blend_factor(ctx->Color.Blend[0].SrcA, GL_TRUE) << - R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.Blend[0].DstA, - GL_FALSE) << - R300_DST_BLEND_SHIFT); - - switch (ctx->Color.Blend[0].EquationA) { - case GL_FUNC_ADD: - eqnA = R300_COMB_FCN_ADD_CLAMP; - break; - - case GL_FUNC_SUBTRACT: - eqnA = R300_COMB_FCN_SUB_CLAMP; - break; - - case GL_FUNC_REVERSE_SUBTRACT: - eqnA = R300_COMB_FCN_RSUB_CLAMP; - break; - - case GL_MIN: - eqnA = R300_COMB_FCN_MIN; - funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); - break; - - case GL_MAX: - eqnA = R300_COMB_FCN_MAX; - funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); - break; - - default: - fprintf(stderr, - "[%s:%u] Invalid A blend equation (0x%04x).\n", - __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationA); - return; - } - - r300SetBlendCntl(r300, - func, eqn, - (R300_SEPARATE_ALPHA_ENABLE | - R300_READ_ENABLE | - R300_ALPHA_BLEND_ENABLE), funcA, eqnA); -} - -static void r300BlendEquationSeparate(struct gl_context * ctx, - GLenum modeRGB, GLenum modeA) -{ - r300SetBlendState(ctx); -} - -static void r300BlendFuncSeparate(struct gl_context * ctx, - GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - r300SetBlendState(ctx); -} - -/** - * Translate LogicOp enums into hardware representation. - * Both use a very logical bit-wise layout, but unfortunately the order - * of bits is reversed. - */ -static GLuint translate_logicop(GLenum logicop) -{ - GLuint bits = logicop - GL_CLEAR; - bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3); - return bits << R300_RB3D_ROPCNTL_ROP_SHIFT; -} - -/** - * Used internally to update the r300->hw hardware state to match the - * current OpenGL state. - */ -static void r300SetLogicOpState(struct gl_context *ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - R300_STATECHANGE(r300, rop); - if (ctx->Color.ColorLogicOpEnabled) { - r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE | - translate_logicop(ctx->Color.LogicOp); - } else { - r300->hw.rop.cmd[1] = 0; - } -} - -/** - * Called by Mesa when an application program changes the LogicOp state - * via glLogicOp. - */ -static void r300LogicOpcode(struct gl_context *ctx, GLenum logicop) -{ - if (ctx->Color.ColorLogicOpEnabled) - r300SetLogicOpState(ctx); -} - -static void r300ClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLint p; - GLint *ip; - - /* no VAP UCP on non-TCL chipsets */ - if (!rmesa->options.hw_tcl_enabled) - return; - - p = (GLint) plane - (GLint) GL_CLIP_PLANE0; - ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - - R300_STATECHANGE( rmesa, vpucp[p] ); - rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3]; -} - -static void r300SetClipPlaneState(struct gl_context * ctx, GLenum cap, GLboolean state) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLuint p; - - /* no VAP UCP on non-TCL chipsets */ - if (!r300->options.hw_tcl_enabled) - return; - - p = cap - GL_CLIP_PLANE0; - R300_STATECHANGE(r300, vap_clip_cntl); - if (state) { - r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p); - r300ClipPlane(ctx, cap, NULL); - } else { - r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p); - } -} - -/** - * Update our tracked culling state based on Mesa's state. - */ -static void r300UpdateCulling(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - uint32_t val = 0; - - if (ctx->Polygon.CullFlag) { - switch (ctx->Polygon.CullFaceMode) { - case GL_FRONT: - val = R300_CULL_FRONT; - break; - case GL_BACK: - val = R300_CULL_BACK; - break; - case GL_FRONT_AND_BACK: - val = R300_CULL_FRONT | R300_CULL_BACK; - break; - default: - break; - } - } - - switch (ctx->Polygon.FrontFace) { - case GL_CW: - val |= R300_FRONT_FACE_CW; - break; - case GL_CCW: - val |= R300_FRONT_FACE_CCW; - break; - default: - break; - } - - /* Winding is inverted when rendering to FBO */ - if (ctx->DrawBuffer && ctx->DrawBuffer->Name) - val ^= R300_FRONT_FACE_CW; - - R300_STATECHANGE(r300, cul); - r300->hw.cul.cmd[R300_CUL_CULL] = val; -} - -static void r300SetPolygonOffsetState(struct gl_context * ctx, GLboolean state) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - R300_STATECHANGE(r300, occlusion_cntl); - if (state) { - r300->hw.occlusion_cntl.cmd[1] |= (3 << 0); - } else { - r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0); - } -} - -static GLboolean current_fragment_program_writes_depth(struct gl_context* ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - return ctx->FragmentProgram._Current && r300->selected_fp->code.writes_depth; -} - -static void r300SetEarlyZState(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLuint topZ = R300_ZTOP_ENABLE; - GLuint w_fmt, fgdepthsrc; - - if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS) - topZ = R300_ZTOP_DISABLE; - else if (current_fragment_program_writes_depth(ctx)) - topZ = R300_ZTOP_DISABLE; - else if (ctx->FragmentProgram._Current && ctx->FragmentProgram._Current->UsesKill) - topZ = R300_ZTOP_DISABLE; - else if (r300->radeon.query.current) - topZ = R300_ZTOP_DISABLE; - - if (topZ != r300->hw.zstencil_format.cmd[2]) { - /* Note: This completely reemits the stencil format. - * I have not tested whether this is strictly necessary, - * or if emitting a write to ZB_ZTOP is enough. - */ - R300_STATECHANGE(r300, zstencil_format); - r300->hw.zstencil_format.cmd[2] = topZ; - } - - /* w_fmt value is set to get best performance - * see p.130 R5xx 3D acceleration guide v1.3 */ - if (current_fragment_program_writes_depth(ctx)) { - fgdepthsrc = R300_FG_DEPTH_SRC_SHADER; - w_fmt = R300_W_FMT_W24 | R300_W_SRC_US; - } else { - fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; - w_fmt = R300_W_FMT_W0 | R300_W_SRC_US; - } - - if (w_fmt != r300->hw.us_out_fmt.cmd[5]) { - R300_STATECHANGE(r300, us_out_fmt); - r300->hw.us_out_fmt.cmd[5] = w_fmt; - } - - if (fgdepthsrc != r300->hw.fg_depth_src.cmd[1]) { - R300_STATECHANGE(r300, fg_depth_src); - r300->hw.fg_depth_src.cmd[1] = fgdepthsrc; - } -} - -static void r300SetAlphaState(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLubyte refByte; - uint32_t pp_misc = 0x0; - GLboolean really_enabled = ctx->Color.AlphaEnabled; - - CLAMPED_FLOAT_TO_UBYTE(refByte, ctx->Color.AlphaRef); - - switch (ctx->Color.AlphaFunc) { - case GL_NEVER: - pp_misc |= R300_FG_ALPHA_FUNC_NEVER; - break; - case GL_LESS: - pp_misc |= R300_FG_ALPHA_FUNC_LESS; - break; - case GL_EQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_EQUAL; - break; - case GL_LEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_LE; - break; - case GL_GREATER: - pp_misc |= R300_FG_ALPHA_FUNC_GREATER; - break; - case GL_NOTEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_NOTEQUAL; - break; - case GL_GEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_GE; - break; - case GL_ALWAYS: - /*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */ - really_enabled = GL_FALSE; - break; - } - - if (really_enabled) { - pp_misc |= R300_FG_ALPHA_FUNC_ENABLE; - pp_misc |= R500_FG_ALPHA_FUNC_8BIT; - pp_misc |= (refByte & R300_FG_ALPHA_FUNC_VAL_MASK); - } else { - pp_misc = 0x0; - } - - R300_STATECHANGE(r300, at); - r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc; - r300->hw.at.cmd[R300_AT_UNKNOWN] = 0; -} - -static void r300AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref) -{ - (void)func; - (void)ref; - r300SetAlphaState(ctx); -} - -static int translate_func(int func) -{ - switch (func) { - case GL_NEVER: - return R300_ZS_NEVER; - case GL_LESS: - return R300_ZS_LESS; - case GL_EQUAL: - return R300_ZS_EQUAL; - case GL_LEQUAL: - return R300_ZS_LEQUAL; - case GL_GREATER: - return R300_ZS_GREATER; - case GL_NOTEQUAL: - return R300_ZS_NOTEQUAL; - case GL_GEQUAL: - return R300_ZS_GEQUAL; - case GL_ALWAYS: - return R300_ZS_ALWAYS; - } - return 0; -} - -static void r300SetDepthState(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - R300_STATECHANGE(r300, zs); - r300->hw.zs.cmd[R300_ZS_CNTL_0] &= (R300_STENCIL_ENABLE | - R300_STENCIL_FRONT_BACK | - R500_STENCIL_REFMASK_FRONT_BACK); - r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT); - - if (ctx->Depth.Test && ctx->DrawBuffer->_DepthBuffer) { - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE; - if (ctx->Depth.Mask) - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE; - r300->hw.zs.cmd[R300_ZS_CNTL_1] |= - translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT; - } -} - -static void r300CatchStencilFallback(struct gl_context *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - const unsigned back = ctx->Stencil._BackFace; - - if (rmesa->radeon.radeonScreen->kernel_mm && - (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)) { - r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE); - } else if (ctx->Stencil._Enabled && - (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back] - || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back] - || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])) { - r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_TRUE); - } else { - r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE); - } -} - -static void r300SetStencilState(struct gl_context * ctx, GLboolean state) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLboolean hw_stencil = GL_FALSE; - - r300CatchStencilFallback(ctx); - - if (ctx->DrawBuffer) { - struct radeon_renderbuffer *rrbStencil - = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); - hw_stencil = (rrbStencil && rrbStencil->bo); - } - - if (hw_stencil) { - R300_STATECHANGE(r300, zs); - if (state) { - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= - R300_STENCIL_ENABLE; - } else { - r300->hw.zs.cmd[R300_ZS_CNTL_0] &= - ~R300_STENCIL_ENABLE; - } - } -} - -static void r300UpdatePolygonMode(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - uint32_t hw_mode = R300_GA_POLY_MODE_DISABLE; - - /* Only do something if a polygon mode is wanted, default is GL_FILL */ - if (ctx->Polygon.FrontMode != GL_FILL || - ctx->Polygon.BackMode != GL_FILL) { - GLenum f, b; - - /* Handle GL_CW (clock wise and GL_CCW (counter clock wise) - * correctly by selecting the correct front and back face - */ - if (ctx->Polygon.FrontFace == GL_CCW) { - f = ctx->Polygon.FrontMode; - b = ctx->Polygon.BackMode; - } else { - f = ctx->Polygon.BackMode; - b = ctx->Polygon.FrontMode; - } - - /* Enable polygon mode */ - hw_mode |= R300_GA_POLY_MODE_DUAL; - - switch (f) { - case GL_LINE: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_LINE; - break; - case GL_POINT: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_POINT; - break; - case GL_FILL: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_TRI; - break; - } - - switch (b) { - case GL_LINE: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_LINE; - break; - case GL_POINT: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_POINT; - break; - case GL_FILL: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_TRI; - break; - } - } - - if (r300->hw.polygon_mode.cmd[1] != hw_mode) { - R300_STATECHANGE(r300, polygon_mode); - r300->hw.polygon_mode.cmd[1] = hw_mode; - } - - r300->hw.polygon_mode.cmd[2] = 0x00000001; - r300->hw.polygon_mode.cmd[3] = 0x00000000; -} - -/** - * Change the culling mode. - * - * \note Mesa already filters redundant calls to this function. - */ -static void r300CullFace(struct gl_context * ctx, GLenum mode) -{ - (void)mode; - - r300UpdateCulling(ctx); -} - -/** - * Change the polygon orientation. - * - * \note Mesa already filters redundant calls to this function. - */ -static void r300FrontFace(struct gl_context * ctx, GLenum mode) -{ - (void)mode; - - r300UpdateCulling(ctx); - r300UpdatePolygonMode(ctx); -} - -/** - * Change the depth testing function. - * - * \note Mesa already filters redundant calls to this function. - */ -static void r300DepthFunc(struct gl_context * ctx, GLenum func) -{ - (void)func; - r300SetDepthState(ctx); -} - -/** - * Enable/Disable depth writing. - * - * \note Mesa already filters redundant calls to this function. - */ -static void r300DepthMask(struct gl_context * ctx, GLboolean mask) -{ - (void)mask; - r300SetDepthState(ctx); -} - -/** - * Handle glColorMask() - */ -static void r300ColorMask(struct gl_context * ctx, - GLboolean r, GLboolean g, GLboolean b, GLboolean a) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) | - (g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) | - (b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) | - (a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0); - - if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) { - R300_STATECHANGE(r300, cmk); - r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask; - } -} - -/* ============================================================= - * Point state - */ -static void r300PointSize(struct gl_context * ctx, GLfloat size) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - /* We need to clamp to user defined range here, because - * the HW clamping happens only for per vertex point size. */ - size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize); - - /* same size limits for AA, non-AA points */ - size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); - - R300_STATECHANGE(r300, ps); - r300->hw.ps.cmd[R300_PS_POINTSIZE] = - ((int)(size * 6) << R300_POINTSIZE_X_SHIFT) | - ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT); -} - -static void r300PointParameter(struct gl_context * ctx, GLenum pname, const GLfloat * param) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - switch (pname) { - case GL_POINT_SIZE_MIN: - R300_STATECHANGE(r300, ga_point_minmax); - r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK; - r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0); - r300PointSize(ctx, ctx->Point.Size); - break; - case GL_POINT_SIZE_MAX: - R300_STATECHANGE(r300, ga_point_minmax); - r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK; - r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0) - << R300_GA_POINT_MINMAX_MAX_SHIFT; - r300PointSize(ctx, ctx->Point.Size); - break; - case GL_POINT_DISTANCE_ATTENUATION: - break; - case GL_POINT_FADE_THRESHOLD_SIZE: - break; - default: - break; - } -} - -/* ============================================================= - * Line state - */ -static void r300LineWidth(struct gl_context * ctx, GLfloat widthf) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - widthf = CLAMP(widthf, - ctx->Const.MinPointSize, - ctx->Const.MaxPointSize); - R300_STATECHANGE(r300, lcntl); - r300->hw.lcntl.cmd[1] = - R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0); -} - -static void r300PolygonMode(struct gl_context * ctx, GLenum face, GLenum mode) -{ - (void)face; - (void)mode; - - r300UpdatePolygonMode(ctx); -} - -/* ============================================================= - * Stencil - */ - -static int translate_stencil_op(int op) -{ - switch (op) { - case GL_KEEP: - return R300_ZS_KEEP; - case GL_ZERO: - return R300_ZS_ZERO; - case GL_REPLACE: - return R300_ZS_REPLACE; - case GL_INCR: - return R300_ZS_INCR; - case GL_DECR: - return R300_ZS_DECR; - case GL_INCR_WRAP_EXT: - return R300_ZS_INCR_WRAP; - case GL_DECR_WRAP_EXT: - return R300_ZS_DECR_WRAP; - case GL_INVERT: - return R300_ZS_INVERT; - default: - WARN_ONCE("Do not know how to translate stencil op"); - return R300_ZS_KEEP; - } - return 0; -} - -static void r300ShadeModel(struct gl_context * ctx, GLenum mode) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - - R300_STATECHANGE(rmesa, shade); - rmesa->hw.shade.cmd[1] = 0x00000002; - R300_STATECHANGE(rmesa, shade2); - switch (mode) { - case GL_FLAT: - rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_FLAT; - break; - case GL_SMOOTH: - rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_SMOOTH; - break; - default: - return; - } - rmesa->hw.shade2.cmd[2] = 0x00000000; - rmesa->hw.shade2.cmd[3] = 0x00000000; -} - -static void r300StencilFuncSeparate(struct gl_context * ctx, GLenum face, - GLenum func, GLint ref, GLuint mask) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLuint refmask; - GLuint flag; - const unsigned back = ctx->Stencil._BackFace; - - r300CatchStencilFallback(ctx); - - refmask = ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT) - | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT); - - R300_STATECHANGE(rmesa, zs); - rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK; - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK << - R300_S_FRONT_FUNC_SHIFT) - | (R300_ZS_MASK << - R300_S_BACK_FUNC_SHIFT)); - - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &= - ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) | - (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT)); - - flag = translate_func(ctx->Stencil.Function[0]); - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (flag << R300_S_FRONT_FUNC_SHIFT); - - flag = translate_func(ctx->Stencil.Function[back]); - - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (flag << R300_S_BACK_FUNC_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask; - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R500_STENCIL_REFMASK_FRONT_BACK; - R300_STATECHANGE(rmesa, zsb); - refmask = ((ctx->Stencil.Ref[back] & 0xff) << R300_STENCILREF_SHIFT) - | ((ctx->Stencil.ValueMask[back] & 0xff) << R300_STENCILMASK_SHIFT); - - rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] &= - ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) | - (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT)); - rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |= refmask; - } -} - -static void r300StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - const unsigned back = ctx->Stencil._BackFace; - - r300CatchStencilFallback(ctx); - - R300_STATECHANGE(rmesa, zs); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &= - ~(R300_STENCILREF_MASK << - R300_STENCILWRITEMASK_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= - (ctx->Stencil. - WriteMask[0] & R300_STENCILREF_MASK) << - R300_STENCILWRITEMASK_SHIFT; - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - R300_STATECHANGE(rmesa, zsb); - rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |= - (ctx->Stencil. - WriteMask[back] & R300_STENCILREF_MASK) << - R300_STENCILWRITEMASK_SHIFT; - } -} - -static void r300StencilOpSeparate(struct gl_context * ctx, GLenum face, - GLenum fail, GLenum zfail, GLenum zpass) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - const unsigned back = ctx->Stencil._BackFace; - - r300CatchStencilFallback(ctx); - - R300_STATECHANGE(rmesa, zs); - /* It is easier to mask what's left.. */ - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= - (R300_ZS_MASK << R300_Z_FUNC_SHIFT) | - (R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) | - (R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT); - - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (translate_stencil_op(ctx->Stencil.FailFunc[0]) << - R300_S_FRONT_SFAIL_OP_SHIFT) - | (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) << - R300_S_FRONT_ZFAIL_OP_SHIFT) - | (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << - R300_S_FRONT_ZPASS_OP_SHIFT); - - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (translate_stencil_op(ctx->Stencil.FailFunc[back]) << - R300_S_BACK_SFAIL_OP_SHIFT) - | (translate_stencil_op(ctx->Stencil.ZFailFunc[back]) << - R300_S_BACK_ZFAIL_OP_SHIFT) - | (translate_stencil_op(ctx->Stencil.ZPassFunc[back]) << - R300_S_BACK_ZPASS_OP_SHIFT); -} - -/* ============================================================= - * Window position and viewport transformation - */ - -static void r300UpdateWindow(struct gl_context * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); - GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; - GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; - const GLfloat *v = ctx->Viewport._WindowMap.m; - const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; - const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0); - GLfloat y_scale, y_bias; - - if (render_to_fbo) { - y_scale = 1.0; - y_bias = 0; - } else { - y_scale = -1.0; - y_bias = yoffset; - } - - GLfloat sx = v[MAT_SX]; - GLfloat tx = v[MAT_TX] + xoffset; - GLfloat sy = v[MAT_SY] * y_scale; - GLfloat ty = (v[MAT_TY] * y_scale) + y_bias; - GLfloat sz = v[MAT_SZ] * depthScale; - GLfloat tz = v[MAT_TZ] * depthScale; - - R300_STATECHANGE(rmesa, vpt); - - rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); - rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx); - rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy); - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty); - rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz); - rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz); -} - -static void r300Viewport(struct gl_context * ctx, GLint x, GLint y, - GLsizei width, GLsizei height) -{ - /* Don't pipeline viewport changes, conflict with window offset - * setting below. Could apply deltas to rescue pipelined viewport - * values, or keep the originals hanging around. - */ - r300UpdateWindow(ctx); - - radeon_viewport(ctx, x, y, width, height); -} - -static void r300DepthRange(struct gl_context * ctx, GLclampd nearval, GLclampd farval) -{ - r300UpdateWindow(ctx); -} - -void r300UpdateViewportOffset(struct gl_context * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); - GLfloat xoffset = (GLfloat) dPriv->x; - GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; - const GLfloat *v = ctx->Viewport._WindowMap.m; - - GLfloat tx = v[MAT_TX] + xoffset; - GLfloat ty = (-v[MAT_TY]) + yoffset; - - if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) || - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) { - /* Note: this should also modify whatever data the context reset - * code uses... - */ - R300_STATECHANGE(rmesa, vpt); - rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx); - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty); - - } - - radeonUpdateScissor(ctx); -} - -/** - * Update R300's own internal state parameters. - * For now just STATE_R300_WINDOW_DIMENSION - */ -static void r300UpdateStateParameters(struct gl_context * ctx, GLuint new_state) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct gl_program_parameter_list *paramList; - - if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS))) - return; - - if (!ctx->FragmentProgram._Current || !rmesa->selected_fp) - return; - - paramList = ctx->FragmentProgram._Current->Base.Parameters; - - if (!paramList) - return; - - _mesa_load_state_parameters(ctx, paramList); -} - -/* ============================================================= - * Polygon state - */ -static void r300PolygonOffset(struct gl_context * ctx, GLfloat factor, GLfloat units) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLfloat constant = units; - - switch (ctx->Visual.depthBits) { - case 16: - constant *= 4.0; - break; - case 24: - constant *= 2.0; - break; - } - - factor *= 12.0; - -/* fprintf(stderr, "%s f:%f u:%f\n", __FUNCTION__, factor, constant); */ - - R300_STATECHANGE(rmesa, zbs); - rmesa->hw.zbs.cmd[R300_ZBS_T_FACTOR] = r300PackFloat32(factor); - rmesa->hw.zbs.cmd[R300_ZBS_T_CONSTANT] = r300PackFloat32(constant); - rmesa->hw.zbs.cmd[R300_ZBS_W_FACTOR] = r300PackFloat32(factor); - rmesa->hw.zbs.cmd[R300_ZBS_W_CONSTANT] = r300PackFloat32(constant); -} - -/* Routing and texture-related */ - -/* r300 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST. - * Since texwrap produces same results for GL_CLAMP and GL_CLAMP_TO_EDGE we use them instead. - * We need to recalculate wrap modes whenever filter mode is changed because someone might do: - * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST); - * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP); - * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); - * Since r300 completely ignores R300_TX_CLAMP when either min or mag is nearest it cant handle - * combinations where only one of them is nearest. - */ -static unsigned long gen_fixed_filter(unsigned long f) -{ - unsigned long mag, min, needs_fixing = 0; - //return f; - - /* We ignore MIRROR bit so we dont have to do everything twice */ - if ((f & ((7 - 1) << R300_TX_WRAP_S_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_S_SHIFT)) { - needs_fixing |= 1; - } - if ((f & ((7 - 1) << R300_TX_WRAP_T_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) { - needs_fixing |= 2; - } - if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) { - needs_fixing |= 4; - } - - if (!needs_fixing) - return f; - - mag = f & R300_TX_MAG_FILTER_MASK; - min = f & (R300_TX_MIN_FILTER_MASK|R300_TX_MIN_FILTER_MIP_MASK); - - /* TODO: Check for anisto filters too */ - if ((mag != R300_TX_MAG_FILTER_NEAREST) - && (min != R300_TX_MIN_FILTER_NEAREST)) - return f; - - /* r300 cant handle these modes hence we force nearest to linear */ - if ((mag == R300_TX_MAG_FILTER_NEAREST) - && (min != R300_TX_MIN_FILTER_NEAREST)) { - f &= ~R300_TX_MAG_FILTER_NEAREST; - f |= R300_TX_MAG_FILTER_LINEAR; - return f; - } - - if ((min == R300_TX_MIN_FILTER_NEAREST) - && (mag != R300_TX_MAG_FILTER_NEAREST)) { - f &= ~R300_TX_MIN_FILTER_NEAREST; - f |= R300_TX_MIN_FILTER_LINEAR; - return f; - } - - /* Both are nearest */ - if (needs_fixing & 1) { - f &= ~((7 - 1) << R300_TX_WRAP_S_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT; - } - if (needs_fixing & 2) { - f &= ~((7 - 1) << R300_TX_WRAP_T_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT; - } - if (needs_fixing & 4) { - f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT; - } - return f; -} - -static void r300SetupFragmentShaderTextures(struct gl_context *ctx, int *tmu_mappings) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int i; - struct r300_fragment_program_code *code = &r300->selected_fp->code.code.r300; - - R300_STATECHANGE(r300, fpt); - - for (i = 0; i < code->tex.length; i++) { - int unit; - int opcode; - unsigned long val; - - unit = code->tex.inst[i] >> R300_TEX_ID_SHIFT; - unit &= 15; - - val = code->tex.inst[i]; - val &= ~R300_TEX_ID_MASK; - - opcode = - (val & R300_TEX_INST_MASK) >> R300_TEX_INST_SHIFT; - if (opcode == R300_TEX_OP_KIL) { - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; - } else { - if (tmu_mappings[unit] >= 0) { - val |= - tmu_mappings[unit] << - R300_TEX_ID_SHIFT; - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; - } else { - // We get here when the corresponding texture image is incomplete - // (e.g. incomplete mipmaps etc.) - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; - } - } - } - - r300->hw.fpt.cmd[R300_FPT_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, - R300_US_TEX_INST_0, code->tex.length); -} - -static void r500SetupFragmentShaderTextures(struct gl_context *ctx, int *tmu_mappings) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - int i; - struct r500_fragment_program_code *code = &r300->selected_fp->code.code.r500; - - /* find all the texture instructions and relocate the texture units */ - for (i = 0; i < code->inst_end + 1; i++) { - if ((code->inst[i].inst0 & 0x3) == R500_INST_TYPE_TEX) { - uint32_t val; - int unit, opcode, new_unit; - - val = code->inst[i].inst1; - - unit = (val >> 16) & 0xf; - - val &= ~(0xf << 16); - - opcode = val & (0x7 << 22); - if (opcode == R500_TEX_INST_TEXKILL) { - new_unit = 0; - } else { - if (tmu_mappings[unit] >= 0) { - new_unit = tmu_mappings[unit]; - } else { - new_unit = 0; - } - } - val |= R500_TEX_ID(new_unit); - code->inst[i].inst1 = val; - } - } -} - -static GLuint translate_lod_bias(GLfloat bias) -{ - GLint b = (int)(bias*32); - if (b >= (1 << 9)) - b = (1 << 9)-1; - else if (b < -(1 << 9)) - b = -(1 << 9); - return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; -} - - -static void r300SetupTextures(struct gl_context * ctx) -{ - int i, mtu; - struct radeon_tex_obj *t; - r300ContextPtr r300 = R300_CONTEXT(ctx); - int hw_tmu = 0; - int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */ - int tmu_mappings[R300_MAX_TEXTURE_UNITS] = { -1, }; - - R300_STATECHANGE(r300, txe); - R300_STATECHANGE(r300, tex.filter); - R300_STATECHANGE(r300, tex.filter_1); - R300_STATECHANGE(r300, tex.size); - R300_STATECHANGE(r300, tex.format); - R300_STATECHANGE(r300, tex.pitch); - R300_STATECHANGE(r300, tex.offset); - R300_STATECHANGE(r300, tex.chroma_key); - R300_STATECHANGE(r300, tex.border_color); - - r300->hw.txe.cmd[R300_TXE_ENABLE] = 0x0; - - mtu = r300->radeon.glCtx->Const.MaxTextureUnits; - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr, "mtu=%d\n", mtu); - - if (mtu > R300_MAX_TEXTURE_UNITS) { - fprintf(stderr, - "Aiiee ! mtu=%d is greater than R300_MAX_TEXTURE_UNITS=%d\n", - mtu, R300_MAX_TEXTURE_UNITS); - exit(-1); - } - - /* We cannot let disabled tmu offsets pass DRM */ - for (i = 0; i < mtu; i++) { - if (ctx->Texture.Unit[i]._ReallyEnabled) { - tmu_mappings[i] = hw_tmu; - - t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); - if (!t) - continue; - - if ((t->pp_txformat & 0xffffff00) == 0xffffff00) { - WARN_ONCE - ("unknown texture format (entry %x) encountered. Help me !\n", - t->pp_txformat & 0xff); - } - - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr, - "Activating texture unit %d\n", i); - - r300->hw.txe.cmd[R300_TXE_ENABLE] |= (1 << hw_tmu); - - r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + - hw_tmu] = - gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28); - /* Note: There is a LOD bias per texture unit and a LOD bias - * per texture object. We add them here to get the correct behaviour. - * (The per-texture object LOD bias was introduced in OpenGL 1.4 - * and is not present in the EXT_texture_object extension). - */ - r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->pp_txfilter_1 | - translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.Sampler.LodBias); - r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->pp_txsize; - r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + - hw_tmu] = t->pp_txformat; - r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] = - t->pp_txpitch; - r300->hw.textures[hw_tmu] = t; - - if (t->tile_bits & R300_TXO_MACRO_TILE) { - WARN_ONCE("macro tiling enabled!\n"); - } - - if (t->tile_bits & R300_TXO_MICRO_TILE) { - WARN_ONCE("micro tiling enabled!\n"); - } - - r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 + - hw_tmu] = 0x0; - r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 + - hw_tmu] = - t->pp_border_color; - - last_hw_tmu = hw_tmu; - - hw_tmu++; - } - } - - /* R3xx and R4xx chips require that the texture unit corresponding to - * KIL instructions is really enabled. - * - * We do some fakery here and in the state atom emit logic to enable - * the texture without tripping up the CS checker in the kernel. - */ - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - if (ctx->FragmentProgram._Current->UsesKill && last_hw_tmu < 0) { - last_hw_tmu++; - - r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; - - r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0] = 0; - r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0] = 0; - r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0; - r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0] = 0; - r300->hw.tex.size.cmd[R300_TEX_VALUE_0] = 0; /* 1x1 texture */ - r300->hw.tex.format.cmd[R300_TEX_VALUE_0] = 0; /* A8 format */ - r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0] = 0; - } - } - - r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1); - r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1); - r300->hw.tex.size.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1); - r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1); - r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1); - r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1); - r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1); - r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1); - - r300->vtbl.SetupFragmentShaderTextures(ctx, tmu_mappings); - - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n", - r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu); -} - -union r300_outputs_written { - GLuint vp_outputs; /* hw_tcl_on */ - DECLARE_RENDERINPUTS(index_bitset); /* !hw_tcl_on */ -}; - -#define R300_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \ - ((hw_tcl_on) ? (ow).vp_outputs & (1 << (vp_result)) : \ - RENDERINPUTS_TEST( (ow.index_bitset), (tnl_attrib) )) - -static void r300SetupRSUnit(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - union r300_outputs_written OutputsWritten; - GLuint InputsRead; - int fp_reg, high_rr; - int col_ip, tex_ip; - int rs_tex_count = 0; - int i, col_fmt, hw_tcl_on; - - hw_tcl_on = r300->options.hw_tcl_enabled; - - if (hw_tcl_on) - OutputsWritten.vp_outputs = r300->selected_vp->code.OutputsWritten; - else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); - - InputsRead = r300->selected_fp->InputsRead; - - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); - - fp_reg = col_ip = tex_ip = col_fmt = 0; - - r300->hw.rc.cmd[1] = 0; - r300->hw.rc.cmd[2] = 0; - for (i=0; i<R300_RR_CMDSIZE-1; ++i) - r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0; - - for (i=0; i<R300_RI_CMDSIZE-1; ++i) - r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0; - - - if (InputsRead & FRAG_BIT_COL0) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL0; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col0, vp doesn't provide it\n"); - } - } - - if (InputsRead & FRAG_BIT_COL1) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL1; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col1, vp doesn't provide it\n"); - } - } - - /* We always route 4 texcoord components */ - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) - continue; - - if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { - WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); - continue; - } - - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~(FRAG_BIT_TEX0 << i); - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } - - /* Setup default color if no color or tex was set */ - if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_ADDR(0); - r300->hw.ri.cmd[R300_RI_INTERP_0] = R300_RS_COL_PTR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001); - ++col_ip; - } - - high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; - r300->hw.rc.cmd[2] |= high_rr - 1; - - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, high_rr); - - if (InputsRead) - WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -} - -static void r500SetupRSUnit(struct gl_context * ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - union r300_outputs_written OutputsWritten; - GLuint InputsRead; - int fp_reg, high_rr; - int col_ip, tex_ip; - int rs_tex_count = 0; - int i, col_fmt, hw_tcl_on; - - hw_tcl_on = r300->options.hw_tcl_enabled; - - if (hw_tcl_on) - OutputsWritten.vp_outputs = r300->selected_vp->code.OutputsWritten; - else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset); - - InputsRead = r300->selected_fp->InputsRead; - - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); - - fp_reg = col_ip = tex_ip = col_fmt = 0; - - r300->hw.rc.cmd[1] = 0; - r300->hw.rc.cmd[2] = 0; - for (i=0; i<R300_RR_CMDSIZE-1; ++i) - r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0; - - for (i=0; i<R500_RI_CMDSIZE-1; ++i) - r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0; - - - if (InputsRead & FRAG_BIT_COL0) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL0; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col0, vp doesn't provide it\n"); - } - } - - if (InputsRead & FRAG_BIT_COL1) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL1; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col1, vp doesn't provide it\n"); - } - } - - /* We always route 4 texcoord components */ - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) - continue; - - if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { - WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); - continue; - } - - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | - ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | - ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | - ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~(FRAG_BIT_TEX0 << i); - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } - - /* Setup default color if no color or tex was set */ - if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] = R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_ADDR(0); - r300->hw.ri.cmd[R300_RI_INTERP_0] = R500_RS_COL_PTR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001); - ++col_ip; - } - - high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] = (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; - r300->hw.rc.cmd[2] = 0xC0 | (high_rr - 1); - - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, high_rr); - - if (InputsRead) - WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -} - - -void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, - GLuint output_count, GLuint temp_count) -{ - int vtx_mem_size; - int pvs_num_slots; - int pvs_num_cntrls; - - /* Flush PVS engine before changing PVS_NUM_SLOTS, PVS_NUM_CNTRLS. - * See r500 docs 6.5.2 - done in emit */ - - /* avoid division by zero */ - if (input_count == 0) input_count = 1; - if (output_count == 0) output_count = 1; - if (temp_count == 0) temp_count = 1; - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - vtx_mem_size = 128; - else - vtx_mem_size = 72; - - pvs_num_slots = MIN3(10, vtx_mem_size/input_count, vtx_mem_size/output_count); - pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count); - - R300_STATECHANGE(rmesa, vap_cntl); - if (rmesa->options.hw_tcl_enabled) { - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = - (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) | - (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) | - (12 << R300_VF_MAX_VTX_NUM_SHIFT); - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION; - } else - /* not sure about non-tcl */ - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (5 << R300_VF_MAX_VTX_NUM_SHIFT)); - - if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R350)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT); - else if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT); - else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT); - else - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT); - -} - -/** - * Enable/Disable states. - * - * \note Mesa already filters redundant calls to this function. - */ -static void r300Enable(struct gl_context * ctx, GLenum cap, GLboolean state) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, - _mesa_lookup_enum_by_nr(cap), - state ? "GL_TRUE" : "GL_FALSE"); - - switch (cap) { - case GL_ALPHA_TEST: - r300SetAlphaState(ctx); - break; - case GL_COLOR_LOGIC_OP: - r300SetLogicOpState(ctx); - /* fall-through, because logic op overrides blending */ - case GL_BLEND: - r300SetBlendState(ctx); - break; - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - r300SetClipPlaneState(ctx, cap, state); - break; - case GL_CULL_FACE: - r300UpdateCulling(ctx); - break; - case GL_DEPTH_TEST: - r300SetDepthState(ctx); - break; - case GL_LINE_SMOOTH: - if (rmesa->options.conformance_mode) - r300SwitchFallback(ctx, R300_FALLBACK_LINE_SMOOTH, ctx->Line.SmoothFlag); - break; - case GL_LINE_STIPPLE: - if (rmesa->options.conformance_mode) - r300SwitchFallback(ctx, R300_FALLBACK_LINE_STIPPLE, ctx->Line.StippleFlag); - break; - case GL_POINT_SMOOTH: - if (rmesa->options.conformance_mode) - r300SwitchFallback(ctx, R300_FALLBACK_POINT_SMOOTH, ctx->Point.SmoothFlag); - break; - case GL_POLYGON_SMOOTH: - if (rmesa->options.conformance_mode) - r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_SMOOTH, ctx->Polygon.SmoothFlag); - break; - case GL_POLYGON_STIPPLE: - if (rmesa->options.conformance_mode) - r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_STIPPLE, ctx->Polygon.StippleFlag); - break; - case GL_POLYGON_OFFSET_POINT: - case GL_POLYGON_OFFSET_LINE: - case GL_POLYGON_OFFSET_FILL: - r300SetPolygonOffsetState(ctx, state); - break; - case GL_SCISSOR_TEST: - radeon_firevertices(&rmesa->radeon); - rmesa->radeon.state.scissor.enabled = state; - radeonUpdateScissor( ctx ); - break; - case GL_STENCIL_TEST: - r300SetStencilState(ctx, state); - break; - default: - break; - } -} - -/** - * Completely recalculates hardware state based on the Mesa state. - */ -static void r300ResetHwState(r300ContextPtr r300) -{ - struct gl_context *ctx = r300->radeon.glCtx; - int has_tcl; - - has_tcl = r300->options.hw_tcl_enabled; - - if (RADEON_DEBUG & RADEON_STATE) - fprintf(stderr, "%s\n", __FUNCTION__); - - r300ColorMask(ctx, - ctx->Color.ColorMask[0][RCOMP], - ctx->Color.ColorMask[0][GCOMP], - ctx->Color.ColorMask[0][BCOMP], - ctx->Color.ColorMask[0][ACOMP]); - - r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); - r300DepthMask(ctx, ctx->Depth.Mask); - r300DepthFunc(ctx, ctx->Depth.Func); - - /* stencil */ - r300Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled); - r300StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]); - r300StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0], - ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]); - r300StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0], - ctx->Stencil.ZFailFunc[0], - ctx->Stencil.ZPassFunc[0]); - - r300UpdateCulling(ctx); - - r300SetBlendState(ctx); - r300SetLogicOpState(ctx); - - r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); - r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); - - r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA - | R300_VPORT_X_OFFSET_ENA - | R300_VPORT_Y_SCALE_ENA - | R300_VPORT_Y_OFFSET_ENA - | R300_VPORT_Z_SCALE_ENA - | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT; - r300->hw.vte.cmd[2] = 0x00000008; - - r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF; - r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000; - -#ifdef MESA_LITTLE_ENDIAN - r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP; -#else - r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP; -#endif - - /* disable VAP/TCL on non-TCL capable chips */ - if (!has_tcl) - r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS; - - r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA; - - /* XXX: Other families? */ - if (has_tcl) { - r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP; - - r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */ - r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */ - r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */ - r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */ - - switch (r300->radeon.radeonScreen->chip_family) { - case CHIP_FAMILY_R300: - r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300; - break; - default: - r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350; - break; - } - } - - r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE - | R300_GB_LINE_STUFF_ENABLE - | R300_GB_TRIANGLE_STUFF_ENABLE; - - r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666; - r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666; - - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = - R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/; - switch (r300->radeon.radeonScreen->num_gb_pipes) { - case 1: - default: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_RV300; - break; - case 2: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R300; - break; - case 3: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R420_3P; - break; - case 4: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R420; - break; - } - - /* XXX: Enable anti-aliasing? */ - r300->hw.gb_misc2.cmd[R300_GB_MISC2_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE; - r300->hw.gb_misc2.cmd[R300_GB_MISC2_SELECT] = 0; - - r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0); - r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0); - r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0); - r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0); - - r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005; - - r300PointSize(ctx, 1.0); - - r300->hw.ga_point_minmax.cmd[1] = 0x18000006; - r300->hw.ga_point_minmax.cmd[2] = 0x00020006; - r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0); - - r300LineWidth(ctx, 1.0); - - r300->hw.ga_line_stipple.cmd[1] = 0; - r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0); - r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0); - - r300ShadeModel(ctx, ctx->Light.ShadeModel); - - r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode); - r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode); - r300->hw.zbias_cntl.cmd[1] = 0x00000000; - - r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor, - ctx->Polygon.OffsetUnits); - r300Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint); - r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine); - r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill); - - r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF; - r300->hw.su_depth_scale.cmd[2] = 0x00000000; - - r300->hw.sc_hyperz.cmd[1] = 0x0000001C; - r300->hw.sc_hyperz.cmd[2] = 0x2DA49525; - - r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF; - - r300->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[5] = R300_W_FMT_W0 | R300_W_SRC_US; - - /* disable fog unit */ - r300->hw.fogs.cmd[R300_FOGS_STATE] = 0; - r300->hw.fg_depth_src.cmd[1] = R300_FG_DEPTH_SRC_SCAN; - - r300->hw.rb3d_cctl.cmd[1] = 0; - - r300BlendColor(ctx, ctx->Color.BlendColor); - - r300->hw.rb3d_dither_ctl.cmd[1] = 0; - r300->hw.rb3d_dither_ctl.cmd[2] = 0; - r300->hw.rb3d_dither_ctl.cmd[3] = 0; - r300->hw.rb3d_dither_ctl.cmd[4] = 0; - r300->hw.rb3d_dither_ctl.cmd[5] = 0; - r300->hw.rb3d_dither_ctl.cmd[6] = 0; - r300->hw.rb3d_dither_ctl.cmd[7] = 0; - r300->hw.rb3d_dither_ctl.cmd[8] = 0; - r300->hw.rb3d_dither_ctl.cmd[9] = 0; - - r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - - r300->hw.zb_depthclearvalue.cmd[1] = 0; - - r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; - r300->hw.zstencil_format.cmd[3] = 0x00000003; - r300->hw.zstencil_format.cmd[4] = 0x00000000; - r300SetEarlyZState(ctx); - - r300->hw.zb_zmask.cmd[1] = 0; - r300->hw.zb_zmask.cmd[2] = 0; - - r300->hw.zb_hiz_offset.cmd[1] = 0; - - r300->hw.zb_hiz_pitch.cmd[1] = 0; - - r300VapCntl(r300, 0, 0, 0); - if (has_tcl) { - r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0; - r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0; - r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0); - r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; - } - - r300->radeon.hw.all_dirty = GL_TRUE; -} - -void r300UpdateShaders(r300ContextPtr rmesa) -{ - struct gl_context *ctx = rmesa->radeon.glCtx; - - /* should only happenen once, just after context is created */ - /* TODO: shouldn't we fallback to sw here? */ - if (!ctx->FragmentProgram._Current) { - fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); - return; - } - - { - struct r300_fragment_program *fp; - - fp = r300SelectAndTranslateFragmentShader(ctx); - - r300SwitchFallback(ctx, R300_FALLBACK_FRAGMENT_PROGRAM, fp->error); - } - - if (rmesa->options.hw_tcl_enabled) { - struct r300_vertex_program *vp; - - vp = r300SelectAndTranslateVertexShader(ctx); - - r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, vp->error); - } - - r300UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); - rmesa->radeon.NewGLState = 0; -} - -static const GLfloat *get_fragmentprogram_constant(struct gl_context *ctx, GLuint index, GLfloat * buffer) -{ - static const GLfloat dummy[4] = { 0, 0, 0, 0 }; - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct rc_constant * rcc = &rmesa->selected_fp->code.constants.Constants[index]; - - switch(rcc->Type) { - case RC_CONSTANT_EXTERNAL: - return &ctx->FragmentProgram._Current->Base.Parameters->ParameterValues[rcc->u.External][0].f; - case RC_CONSTANT_IMMEDIATE: - return rcc->u.Immediate; - case RC_CONSTANT_STATE: - switch(rcc->u.State[0]) { - case RC_STATE_SHADOW_AMBIENT: { - const int unit = (int) rcc->u.State[1]; - const struct gl_texture_object *texObj = ctx->Texture.Unit[unit]._Current; - if (texObj) { - buffer[0] = - buffer[1] = - buffer[2] = - buffer[3] = texObj->Sampler.CompareFailValue; - } - return buffer; - } - - case RC_STATE_R300_WINDOW_DIMENSION: { - __DRIdrawable * drawable = radeon_get_drawable(&rmesa->radeon); - buffer[0] = drawable->w * 0.5f; /* width*0.5 */ - buffer[1] = drawable->h * 0.5f; /* height*0.5 */ - buffer[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */ - buffer[3] = 1.0F; /* not used */ - return buffer; - } - - case RC_STATE_R300_TEXRECT_FACTOR: { - struct gl_texture_object *t = - ctx->Texture.Unit[rcc->u.State[1]].CurrentTex[TEXTURE_RECT_INDEX]; - - if (t && t->Image[0][t->BaseLevel]) { - struct gl_texture_image *image = - t->Image[0][t->BaseLevel]; - buffer[0] = 1.0 / image->Width2; - buffer[1] = 1.0 / image->Height2; - } else { - buffer[0] = 1.0; - buffer[1] = 1.0; - } - buffer[2] = 1.0; - buffer[3] = 1.0; - return buffer; - } - } - } - - return dummy; -} - - -static void r300SetupPixelShader(struct gl_context *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_fragment_program *fp = rmesa->selected_fp; - struct r300_fragment_program_code *code; - int i; - - code = &fp->code.code.r300; - - R300_STATECHANGE(rmesa, fpi[0]); - R300_STATECHANGE(rmesa, fpi[1]); - R300_STATECHANGE(rmesa, fpi[2]); - R300_STATECHANGE(rmesa, fpi[3]); - rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length); - rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length); - rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length); - rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length); - for (i = 0; i < code->alu.length; i++) { - rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].rgb_inst; - rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].rgb_addr; - rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].alpha_inst; - rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].alpha_addr; - } - - R300_STATECHANGE(rmesa, fp); - rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->config; - rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->pixsize; - rmesa->hw.fp.cmd[R300_FP_CNTL2] = code->code_offset; - for (i = 0; i < 4; i++) - rmesa->hw.fp.cmd[R300_FP_NODE0 + i] = code->code_addr[i]; - - R300_STATECHANGE(rmesa, fpp); - rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, fp->code.constants.Count * 4); - for (i = 0; i < fp->code.constants.Count; i++) { - GLfloat buffer[4]; - const GLfloat *constant = get_fragmentprogram_constant(ctx, i, buffer); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]); - } -} - -#define bump_r500fp_count(ptr, new_count) do{\ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ - int _nc=(new_count)/6; \ - assert(_nc < 256); \ - if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ -} while(0) - -#define bump_r500fp_const_count(ptr, new_count) do{\ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ - int _nc=(new_count)/4; \ - assert(_nc < 256); \ - if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ -} while(0) - -static void r500SetupPixelShader(struct gl_context *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_fragment_program *fp = rmesa->selected_fp; - int i; - struct r500_fragment_program_code *code; - - ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0; - - code = &fp->code.code.r500; - - R300_STATECHANGE(rmesa, fp); - rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx; - - rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] = - R500_US_CODE_START_ADDR(0) | - R500_US_CODE_END_ADDR(code->inst_end); - rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] = - R500_US_CODE_RANGE_ADDR(0) | - R500_US_CODE_RANGE_SIZE(code->inst_end); - rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] = - R500_US_CODE_OFFSET_ADDR(0); - - R300_STATECHANGE(rmesa, r500fp); - /* Emit our shader... */ - for (i = 0; i < code->inst_end+1; i++) { - rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0; - rmesa->hw.r500fp.cmd[i*6+2] = code->inst[i].inst1; - rmesa->hw.r500fp.cmd[i*6+3] = code->inst[i].inst2; - rmesa->hw.r500fp.cmd[i*6+4] = code->inst[i].inst3; - rmesa->hw.r500fp.cmd[i*6+5] = code->inst[i].inst4; - rmesa->hw.r500fp.cmd[i*6+6] = code->inst[i].inst5; - } - - bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6); - - R300_STATECHANGE(rmesa, r500fp_const); - for (i = 0; i < fp->code.constants.Count; i++) { - GLfloat buffer[4]; - const GLfloat *constant = get_fragmentprogram_constant(ctx, i, buffer); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]); - } - bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, fp->code.constants.Count * 4); -} - -void r300SetupVAP(struct gl_context *ctx, GLuint InputsRead, GLuint OutputsWritten) -{ - r300ContextPtr rmesa = R300_CONTEXT( ctx ); - struct vertex_attribute *attrs = rmesa->vbuf.attribs; - int i, j, reg_count; - uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; - uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; - - for (i = 0; i < R300_VIR_CMDSIZE-1; ++i) - vir0[i] = vir1[i] = 0; - - for (i = 0, j = 0; i < rmesa->vbuf.num_attribs; ++i) { - int tmp; - - tmp = attrs[i].data_type | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT); - if (attrs[i]._signed) - tmp |= R300_SIGNED; - if (attrs[i].normalize) - tmp |= R300_NORMALIZE; - - if (i % 2 == 0) { - vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT; - vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT); - } else { - vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT; - vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; - ++j; - } - } - - reg_count = (rmesa->vbuf.num_attribs + 1) >> 1; - if (rmesa->vbuf.num_attribs % 2 != 0) { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; - } else { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; - } - - R300_STATECHANGE(rmesa, vir[0]); - R300_STATECHANGE(rmesa, vir[1]); - R300_STATECHANGE(rmesa, vof); - R300_STATECHANGE(rmesa, vic); - - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16; - rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16; - } else { - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count; - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; - } - - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); -} - -void r300UpdateShaderStates(r300ContextPtr rmesa) -{ - struct gl_context *ctx; - ctx = rmesa->radeon.glCtx; - - /* should only happenen once, just after context is created */ - if (!ctx->FragmentProgram._Current) - return; - - r300SetEarlyZState(ctx); - - r300SetupTextures(ctx); - - rmesa->vtbl.SetupPixelShader(ctx); - - rmesa->vtbl.SetupRSUnit(ctx); - - if (rmesa->options.hw_tcl_enabled) { - r300SetupVertexProgram(rmesa); - } -} - -#define EASY_US_OUT_FMT(comps, c0, c1, c2, c3) \ - (R500_OUT_FMT_##comps | R500_C0_SEL_##c0 | R500_C1_SEL_##c1 | \ - R500_C2_SEL_##c2 | R500_C3_SEL_##c3) -static void r300SetupUsOutputFormat(struct gl_context *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - uint32_t hw_format; - struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&rmesa->radeon); - - if (!rrb) { - return; - } - - switch (rrb->base.Format) - { - case MESA_FORMAT_RGBA5551: - case MESA_FORMAT_RGBA8888: - hw_format = EASY_US_OUT_FMT(C4_8, A, B, G, R); - break; - case MESA_FORMAT_RGB565_REV: - case MESA_FORMAT_RGBA8888_REV: - hw_format = EASY_US_OUT_FMT(C4_8, R, G, B, A); - break; - case MESA_FORMAT_RGB565: - case MESA_FORMAT_ARGB4444: - case MESA_FORMAT_ARGB1555: - case MESA_FORMAT_XRGB8888: - case MESA_FORMAT_ARGB8888: - hw_format = EASY_US_OUT_FMT(C4_8, B, G, R, A); - break; - case MESA_FORMAT_ARGB4444_REV: - case MESA_FORMAT_ARGB1555_REV: - case MESA_FORMAT_XRGB8888_REV: - case MESA_FORMAT_ARGB8888_REV: - hw_format = EASY_US_OUT_FMT(C4_8, A, R, G, B); - break; - case MESA_FORMAT_SRGBA8: - hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, A, B, G, R); - break; - case MESA_FORMAT_SARGB8: - hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, B, G, R, A); - break; - case MESA_FORMAT_SL8: - hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, A, A, R, A); - break; - case MESA_FORMAT_A8: - hw_format = EASY_US_OUT_FMT(C4_8, A, A, A, A); - break; - case MESA_FORMAT_L8: - case MESA_FORMAT_I8: - hw_format = EASY_US_OUT_FMT(C4_8, A, A, R, A); - break; - default: - assert(!"Unsupported format"); - hw_format = 0; - break; - } - - R300_STATECHANGE(rmesa, us_out_fmt); - rmesa->hw.us_out_fmt.cmd[1] = hw_format; -} -#undef EASY_US_OUT_FMT - -/** - * Called by Mesa after an internal state update. - */ -static void r300InvalidateState(struct gl_context * ctx, GLuint new_state) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - - _swrast_InvalidateState(ctx, new_state); - _swsetup_InvalidateState(ctx, new_state); - _vbo_InvalidateState(ctx, new_state); - _tnl_InvalidateState(ctx, new_state); - - if (new_state & _NEW_BUFFERS) { - _mesa_update_framebuffer(ctx); - /* this updates the DrawBuffer's Width/Height if it's a FBO */ - _mesa_update_draw_buffer_bounds(ctx); - - R300_STATECHANGE(r300, cb); - R300_STATECHANGE(r300, zb); - } - - if (new_state & (_NEW_LIGHT)) { - R300_STATECHANGE(r300, shade2); - if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) - r300->hw.shade2.cmd[1] |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST; - else - r300->hw.shade2.cmd[1] &= ~R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST; - } - - if (new_state & _NEW_BUFFERS) { - r300SetupUsOutputFormat(ctx); - } - - r300->radeon.NewGLState |= new_state; -} - -/** - * Calculate initial hardware state and register state functions. - * Assumes that the command buffer and state atoms have been - * initialized already. - */ -void r300InitState(r300ContextPtr r300) -{ - r300ResetHwState(r300); -} - -static void r300RenderMode(struct gl_context * ctx, GLenum mode) -{ - r300SwitchFallback(ctx, R300_FALLBACK_RENDER_MODE, ctx->RenderMode != GL_RENDER); -} - -/** - * Initialize driver's state callback functions - */ -void r300InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions) -{ - - functions->UpdateState = r300InvalidateState; - functions->AlphaFunc = r300AlphaFunc; - functions->BlendColor = r300BlendColor; - functions->BlendEquationSeparate = r300BlendEquationSeparate; - functions->BlendFuncSeparate = r300BlendFuncSeparate; - functions->Enable = r300Enable; - functions->ColorMask = r300ColorMask; - functions->DepthFunc = r300DepthFunc; - functions->DepthMask = r300DepthMask; - functions->CullFace = r300CullFace; - functions->FrontFace = r300FrontFace; - functions->ShadeModel = r300ShadeModel; - functions->LogicOpcode = r300LogicOpcode; - - /* ARB_point_parameters */ - functions->PointParameterfv = r300PointParameter; - - /* Stencil related */ - functions->StencilFuncSeparate = r300StencilFuncSeparate; - functions->StencilMaskSeparate = r300StencilMaskSeparate; - functions->StencilOpSeparate = r300StencilOpSeparate; - - /* Viewport related */ - functions->Viewport = r300Viewport; - functions->DepthRange = r300DepthRange; - functions->PointSize = r300PointSize; - functions->LineWidth = r300LineWidth; - - functions->PolygonOffset = r300PolygonOffset; - functions->PolygonMode = r300PolygonMode; - - functions->RenderMode = r300RenderMode; - - functions->ClipPlane = r300ClipPlane; - functions->Scissor = radeonScissor; - - functions->DrawBuffer = radeonDrawBuffer; - functions->ReadBuffer = radeonReadBuffer; - - functions->CopyPixels = _mesa_meta_CopyPixels; - functions->DrawPixels = _mesa_meta_DrawPixels; - if (radeon->radeonScreen->kernel_mm) - functions->ReadPixels = radeonReadPixels; -} - -void r300InitShaderFunctions(r300ContextPtr r300) -{ - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r300->vtbl.SetupRSUnit = r500SetupRSUnit; - r300->vtbl.SetupPixelShader = r500SetupPixelShader; - r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures; - } else { - r300->vtbl.SetupRSUnit = r300SetupRSUnit; - r300->vtbl.SetupPixelShader = r300SetupPixelShader; - r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures; - } -} diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h deleted file mode 100644 index e3b0da4cbde..00000000000 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ /dev/null @@ -1,62 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Nicolai Haehnle <[email protected]> - */ - -#ifndef __R300_STATE_H__ -#define __R300_STATE_H__ - -#include "r300_context.h" - -#define R300_NEWPRIM( rmesa ) \ - do { \ - if ( rmesa->radeon.dma.flush ) \ - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ - } while (0) - -#define R300_STATECHANGE(r300, atom) \ - do { \ - R300_NEWPRIM(r300); \ - r300->hw.atom.dirty = GL_TRUE; \ - r300->radeon.hw.is_dirty = GL_TRUE; \ - } while(0) - -void r300UpdateViewportOffset (struct gl_context * ctx); -void r300UpdateDrawBuffer (struct gl_context * ctx); -void r300UpdateShaders (r300ContextPtr rmesa); -void r300UpdateShaderStates (r300ContextPtr rmesa); -void r300InitState (r300ContextPtr r300); -void r300InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions); -void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count); -void r300SetupVAP(struct gl_context *ctx, GLuint InputsRead, GLuint OutputsWritten); - -#endif /* __R300_STATE_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c deleted file mode 100644 index 4a6762ff830..00000000000 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ /dev/null @@ -1,683 +0,0 @@ -/************************************************************************** - -Copyright (C) 2007 Dave Airlie - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Dave Airlie <[email protected]> - * Maciej Cencora <[email protected]> - */ - -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -#include "r300_state.h" -#include "r300_swtcl.h" -#include "r300_emit.h" -#include "r300_tex.h" -#include "r300_render.h" -#include "main/simple_list.h" - -#define EMIT_ATTR( ATTR, STYLE ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ -} while (0) - -#define EMIT_PAD( N ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ -} while (0) - -#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask, _normalize) \ -do { \ - attrs[num_attrs].element = (_attr); \ - attrs[num_attrs].data_type = (_format); \ - attrs[num_attrs].dst_loc = (_dst_loc); \ - attrs[num_attrs].swizzle = (_swizzle); \ - attrs[num_attrs].write_mask = (_write_mask); \ - attrs[num_attrs]._signed = 0; \ - attrs[num_attrs].normalize = (_normalize); \ - ++num_attrs; \ -} while (0) - -void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *_InputsRead, GLuint *_OutputsWritten) -{ - r300ContextPtr rmesa = R300_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - int first_free_tex = 0; - GLuint InputsRead = 0; - GLuint OutputsWritten = 0; - int num_attrs = 0; - GLuint fp_reads = rmesa->selected_fp->InputsRead; - struct vertex_attribute *attrs = rmesa->vbuf.attribs; - - radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__); - rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; - rmesa->radeon.swtcl.vertex_attr_count = 0; - - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); - - /* We always want non Ndc coords format */ - VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - - /* Always write position vector */ - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0); - rmesa->swtcl.coloroffset = 4; - - if (fp_reads & FRAG_BIT_COL0) { - InputsRead |= 1 << VERT_ATTRIB_COLOR0; - OutputsWritten |= 1 << VERT_RESULT_COL0; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1); -#else - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1); -#endif - } - - if (fp_reads & FRAG_BIT_COL1) { - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - InputsRead |= 1 << VERT_ATTRIB_COLOR1; - OutputsWritten |= 1 << VERT_RESULT_COL1; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1); -#else - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1); -#endif - rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1; - } - - if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) { - VB->AttribPtr[VERT_ATTRIB_GENERIC0] = VB->BackfaceColorPtr; - OutputsWritten |= 1 << VERT_RESULT_BFC0; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1); -#else - EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1); -#endif - if (fp_reads & FRAG_BIT_COL1) { - VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->BackfaceSecondaryColorPtr; - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - OutputsWritten |= 1 << VERT_RESULT_BFC1; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1); -#else - EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1); -#endif - } - } - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) { - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); - InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE; - OutputsWritten |= 1 << VERT_RESULT_PSIZ; - EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_POINT_SIZE, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_POINT_SIZE, swiz, MASK_X, 0); - } - - if (rmesa->selected_fp->wpos_attr != FRAG_ATTRIB_MAX) { - int tex_id = rmesa->selected_fp->wpos_attr - FRAG_ATTRIB_TEX0; - - VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS]; - VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS]; - RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id); - } - - if (rmesa->selected_fp->fog_attr != FRAG_ATTRIB_MAX) { - int tex_id = rmesa->selected_fp->fog_attr - FRAG_ATTRIB_TEX0; - - VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG]; - VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG]; - RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id); - } - - /** - * Sending only one texcoord component may lead to lock up, - * so for all textures always output 4 texcoord components to RS. - */ - { - int i; - GLuint swiz, format, hw_format; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (fp_reads & FRAG_BIT_TEX(i)) { - switch (VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size) { - case 1: - format = EMIT_1F; - hw_format = R300_DATA_TYPE_FLOAT_1; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE); - break; - case 2: - format = EMIT_2F; - hw_format = R300_DATA_TYPE_FLOAT_2; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE); - break; - case 3: - format = EMIT_3F; - hw_format = R300_DATA_TYPE_FLOAT_3; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - break; - case 4: - format = EMIT_4F; - hw_format = R300_DATA_TYPE_FLOAT_4; - swiz = SWIZZLE_XYZW; - break; - default: - continue; - } - InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); - OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); - EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); - ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0); - ++first_free_tex; - } - } - } - - if (first_free_tex >= ctx->Const.MaxTextureUnits) { - fprintf(stderr, "\tout of free texcoords to write fog coordinate\n"); - exit(-1); - } - - R300_NEWPRIM(rmesa); - rmesa->vbuf.num_attribs = num_attrs; - *_InputsRead = InputsRead; - *_OutputsWritten = OutputsWritten; - - RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset); -} - -static void r300PrepareVertices(struct gl_context *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLuint InputsRead, OutputsWritten; - radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__); - - r300ChooseSwtclVertexFormat(ctx, &InputsRead, &OutputsWritten); - r300SetupVAP(ctx, InputsRead, OutputsWritten); - - rmesa->radeon.swtcl.vertex_size = - _tnl_install_attrs( ctx, - rmesa->radeon.swtcl.vertex_attrs, - rmesa->radeon.swtcl.vertex_attr_count, - NULL, 0 ); - - rmesa->radeon.swtcl.vertex_size /= 4; -} - -static void r300_predict_emit_size( r300ContextPtr rmesa ) -{ - if (!rmesa->radeon.swtcl.emit_prediction) { - const int vertex_size = 7; - const int prim_size = 3; - const int cache_flush_size = 4; - const int pre_emit_state = 4; - const int scissor_size = 3; - const int state_size = radeonCountStateEmitSize(&rmesa->radeon); - - if (rcommonEnsureCmdBufSpace(&rmesa->radeon, - state_size + pre_emit_state + scissor_size - + vertex_size + prim_size + cache_flush_size * 2, - __FUNCTION__)) - rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize(&rmesa->radeon); - else - rmesa->radeon.swtcl.emit_prediction = state_size; - - rmesa->radeon.swtcl.emit_prediction += rmesa->radeon.cmdbuf.cs->cdw - + vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state; - radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, - "%s, size %d\n", - __func__, rmesa->radeon.cmdbuf.cs->cdw - + vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state); - } -} - - -static GLuint reduced_prim[] = { - GL_POINTS, - GL_LINES, - GL_LINES, - GL_LINES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, -}; - -static void r300RasterPrimitive( struct gl_context *ctx, GLuint prim ); - -/*********************************************************************** - * Emit primitives as inline vertices * - ***********************************************************************/ - - -#define HAVE_POINTS 1 -#define HAVE_LINES 1 -#define HAVE_LINE_STRIPS 1 -#define HAVE_TRIANGLES 1 -#define HAVE_TRI_STRIPS 1 -#define HAVE_TRI_STRIP_1 0 -#define HAVE_TRI_FANS 1 -#define HAVE_QUADS 0 -#define HAVE_QUAD_STRIPS 0 -#define HAVE_POLYGONS 1 -#define HAVE_ELTS 1 - -static void* r300_alloc_verts(r300ContextPtr rmesa, GLuint n, GLuint size) -{ - void *rv; - do { - r300_predict_emit_size( rmesa ); - rv = rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ); - } while (!rv); - return rv; -} - -#undef LOCAL_VARS -#undef ALLOC_VERTS -#define CTX_ARG r300ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r300_alloc_verts(rmesa, n, size); -#define LOCAL_VARS \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const char *r300verts = (char *)rmesa->radeon.swtcl.verts; -#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) -#define VERTEX r300Vertex -#undef TAG -#define TAG(x) r300_##x -#include "tnl_dd/t_dd_triemit.h" - - - -/*********************************************************************** - * Macros for t_dd_tritmp.h to draw basic primitives * - ***********************************************************************/ - -#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d ) -#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c ) -#define LINE( a, b ) r300_line( rmesa, a, b ) -#define POINT( a ) r300_point( rmesa, a ) - -/*********************************************************************** - * Build render functions from dd templates * - ***********************************************************************/ - -#define R300_UNFILLED_BIT 0x01 -#define R300_MAX_TRIFUNC 0x02 - -static struct { - tnl_points_func points; - tnl_line_func line; - tnl_triangle_func triangle; - tnl_quad_func quad; -} rast_tab[R300_MAX_TRIFUNC]; - -#define DO_FALLBACK 0 -#define DO_UNFILLED (IND & R300_UNFILLED_BIT) -#define DO_TWOSIDE 0 -#define DO_FLAT 0 -#define DO_OFFSET 0 -#define DO_TRI 1 -#define DO_QUAD 1 -#define DO_LINE 1 -#define DO_POINTS 1 -#define DO_FULL_QUAD 1 - -#define HAVE_SPEC 1 -#define HAVE_BACK_COLORS 0 -#define HAVE_HW_FLATSHADE 1 -#define TAB rast_tab - -#define DEPTH_SCALE 1.0 -#define UNFILLED_TRI unfilled_tri -#define UNFILLED_QUAD unfilled_quad -#define VERT_X(_v) _v->v.x -#define VERT_Y(_v) _v->v.y -#define VERT_Z(_v) _v->v.z -#define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) - -#define VERT_SET_RGBA( v, c ) \ -do { \ - r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ -} while (0) - -#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] - -#define VERT_SET_SPEC( v0, c ) \ -do { \ - if (specoffset) { \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \ - } \ -} while (0) - -#define VERT_COPY_SPEC( v0, v1 ) \ -do { \ - if (specoffset) { \ - v0->v.specular.red = v1->v.specular.red; \ - v0->v.specular.green = v1->v.specular.green; \ - v0->v.specular.blue = v1->v.specular.blue; \ - } \ -} while (0) - -#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] -#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] -#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] -#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] - -#undef LOCAL_VARS -#undef TAG -#undef INIT - -#define LOCAL_VARS(n) \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - GLuint color[n] = { 0, }, spec[n] = { 0, }; \ - GLuint coloroffset = rmesa->swtcl.coloroffset; \ - GLuint specoffset = rmesa->swtcl.specoffset; \ - (void) color; (void) spec; (void) coloroffset; (void) specoffset; - -/*********************************************************************** - * Helpers for rendering unfilled primitives * - ***********************************************************************/ - -#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] ) -#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive -#undef TAG -#define TAG(x) x -#include "tnl_dd/t_dd_unfilled.h" -#undef IND - - -/*********************************************************************** - * Generate GL render functions * - ***********************************************************************/ - - -#define IND (0) -#define TAG(x) x -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R300_UNFILLED_BIT) -#define TAG(x) x##_unfilled -#include "tnl_dd/t_dd_tritmp.h" - - -static void init_rast_tab( void ) -{ - init(); - init_unfilled(); -} - -/**********************************************************************/ -/* Render unclipped begin/end objects */ -/**********************************************************************/ - -#define RENDER_POINTS( start, count ) \ - for ( ; start < count ; start++) \ - r300_point( rmesa, VERT(start) ) -#define RENDER_LINE( v0, v1 ) \ - r300_line( rmesa, VERT(v0), VERT(v1) ) -#define RENDER_TRI( v0, v1, v2 ) \ - r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) -#define RENDER_QUAD( v0, v1, v2, v3 ) \ - r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) -#define INIT(x) do { \ - r300RenderPrimitive( ctx, x ); \ -} while (0) -#undef LOCAL_VARS -#define LOCAL_VARS \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ - const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \ - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ - const GLboolean stipple = ctx->Line.StippleFlag; \ - (void) elt; (void) stipple; -#define RESET_STIPPLE //if ( stipple ) r200ResetLineStipple( ctx ); -#define RESET_OCCLUSION -#define PRESERVE_VB_DEFS -#define ELT(x) (x) -#define TAG(x) r300_##x##_verts -#include "tnl/t_vb_rendertmp.h" -#undef ELT -#undef TAG -#define TAG(x) r300_##x##_elts -#define ELT(x) elt[x] -#include "tnl/t_vb_rendertmp.h" - - - - -/**********************************************************************/ -/* Choose render functions */ -/**********************************************************************/ -static void r300ChooseRenderState( struct gl_context *ctx ) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); - GLuint index = 0; - GLuint flags = ctx->_TriangleCaps; - radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__); - - if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; - - if (index != rmesa->radeon.swtcl.RenderIndex) { - tnl->Driver.Render.Points = rast_tab[index].points; - tnl->Driver.Render.Line = rast_tab[index].line; - tnl->Driver.Render.ClippedLine = rast_tab[index].line; - tnl->Driver.Render.Triangle = rast_tab[index].triangle; - tnl->Driver.Render.Quad = rast_tab[index].quad; - - if (index == 0) { - tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts; - tnl->Driver.Render.PrimTabElts = r300_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly; - } else { - tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; - tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; - } - - rmesa->radeon.swtcl.RenderIndex = index; - } -} - -void r300RenderStart(struct gl_context *ctx) -{ - radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__); - r300ContextPtr rmesa = R300_CONTEXT( ctx ); - - r300ChooseRenderState(ctx); - - r300UpdateShaders(rmesa); - - r300PrepareVertices(ctx); - - r300ValidateBuffers(ctx); - - r300UpdateShaderStates(rmesa); - - - /* investigate if we can put back flush optimisation if needed */ - if (rmesa->radeon.dma.flush != NULL) { - rmesa->radeon.dma.flush(ctx); - } -} - -void r300RenderFinish(struct gl_context *ctx) -{ -} - -static void r300RasterPrimitive( struct gl_context *ctx, GLuint hwprim ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__); - - if (rmesa->radeon.swtcl.hw_primitive != hwprim) { - R300_NEWPRIM( rmesa ); - rmesa->radeon.swtcl.hw_primitive = hwprim; - } -} - -void r300RenderPrimitive(struct gl_context *ctx, GLenum prim) -{ - - r300ContextPtr rmesa = R300_CONTEXT(ctx); - rmesa->radeon.swtcl.render_primitive = prim; - radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__); - - if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) - return; - - r300RasterPrimitive( ctx, reduced_prim[prim] ); -} - -void r300ResetLineStipple(struct gl_context *ctx) -{ - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); -} - -void r300InitSwtcl(struct gl_context *ctx) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); - static int firsttime = 1; - radeon_print(RADEON_SWRENDER, RADEON_NORMAL, "%s\n", __func__); - - if (firsttime) { - init_rast_tab(); - firsttime = 0; - } - rmesa->radeon.swtcl.emit_prediction = 0; - - tnl->Driver.Render.Start = r300RenderStart; - tnl->Driver.Render.Finish = r300RenderFinish; - tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - /* FIXME: what are these numbers? */ - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, - 48 * sizeof(GLfloat) ); - - rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; - rmesa->radeon.swtcl.hw_primitive = 0; - - _tnl_invalidate_vertex_state( ctx, ~0 ); - _tnl_invalidate_vertices( ctx, ~0 ); - - _tnl_need_projected_coords( ctx, GL_FALSE ); -} - -void r300DestroySwtcl(struct gl_context *ctx) -{ -} - -static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) -{ - BATCH_LOCALS(&rmesa->radeon); - - radeon_print(RADEON_SWRENDER, RADEON_TRACE, - "%s: vertex_size %d, offset 0x%x \n", - __FUNCTION__, vertex_size, offset); - - BEGIN_BATCH(7); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); -} - -static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) -{ - BATCH_LOCALS(&rmesa->radeon); - int type, num_verts; - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); - - type = r300PrimitiveType(rmesa, primitive); - num_verts = r300NumVerts(rmesa, vertex_nr, primitive); - - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); - END_BATCH(); -} - -void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset) -{ - radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__); - r300ContextPtr rmesa = R300_CONTEXT(ctx); - - r300EmitCacheFlush(rmesa); - - radeonEmitState(&rmesa->radeon); - r300_emit_scissor(ctx); - r300EmitVertexAOS(rmesa, - rmesa->radeon.swtcl.vertex_size, - rmesa->radeon.swtcl.bo, - current_offset); - - r300EmitVbufPrim(rmesa, - rmesa->radeon.swtcl.hw_primitive, - rmesa->radeon.swtcl.numverts); - r300EmitCacheFlush(rmesa); - if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw ) - WARN_ONCE("Rendering was %d commands larger than predicted size." - " We might overflow command buffer.\n", - rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction ); - rmesa->radeon.swtcl.emit_prediction = 0; - COMMIT_BATCH(); -} diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h deleted file mode 100644 index 51cfffc2af2..00000000000 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ /dev/null @@ -1,65 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell <[email protected]> - original r200 code - * Dave Airlie <[email protected]> - */ - -#ifndef __R300_SWTCL_H__ -#define __R300_SWTCL_H__ - -#include "main/mtypes.h" -#include "swrast/swrast.h" -#include "r300_context.h" - -/* - * Here are definitions of OVM locations of vertex attributes for non TCL hw - */ -#define SWTCL_OVM_POS 0 -#define SWTCL_OVM_COLOR0 2 -#define SWTCL_OVM_COLOR1 3 -#define SWTCL_OVM_COLOR2 4 -#define SWTCL_OVM_COLOR3 5 -#define SWTCL_OVM_TEX(n) ((n) + 6) -#define SWTCL_OVM_POINT_SIZE 15 - -extern void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *InputsRead, GLuint *OutputsWritten); - -extern void r300InitSwtcl( struct gl_context *ctx ); -extern void r300DestroySwtcl( struct gl_context *ctx ); - -extern void r300RenderStart(struct gl_context *ctx); -extern void r300RenderFinish(struct gl_context *ctx); -extern void r300RenderPrimitive(struct gl_context *ctx, GLenum prim); -extern void r300ResetLineStipple(struct gl_context *ctx); - -extern void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset); - -#endif diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c deleted file mode 100644 index 10e9d99b0ed..00000000000 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ /dev/null @@ -1,369 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/** - * \file - * - * \author Keith Whitwell <[email protected]> - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/colormac.h" -#include "main/context.h" -#include "main/enums.h" -#include "main/image.h" -#include "main/mfeatures.h" -#include "main/mipmap.h" -#include "main/simple_list.h" -#include "main/texobj.h" - -#include "texmem.h" - -#include "r300_context.h" -#include "radeon_mipmap_tree.h" -#include "r300_tex.h" - - -static unsigned int translate_wrap_mode(GLenum wrapmode) -{ - switch(wrapmode) { - case GL_REPEAT: return R300_TX_REPEAT; - case GL_CLAMP: return R300_TX_CLAMP; - case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE; - case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER; - case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; - default: - _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); - return 0; - } -} - - -/** - * Update the cached hardware registers based on the current texture wrap modes. - * - * \param t Texture object whose wrap modes are to be set - */ -static void r300UpdateTexWrap(radeonTexObjPtr t) -{ - struct gl_texture_object *tObj = &t->base; - - t->pp_txfilter &= - ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK); - - t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapS) << R300_TX_WRAP_S_SHIFT; - - if (tObj->Target != GL_TEXTURE_1D) { - t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapT) << R300_TX_WRAP_T_SHIFT; - - if (tObj->Target == GL_TEXTURE_3D) - t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapR) << R300_TX_WRAP_R_SHIFT; - } -} - -static GLuint aniso_filter(GLfloat anisotropy) -{ - if (anisotropy >= 16.0) { - return R300_TX_MAX_ANISO_16_TO_1; - } else if (anisotropy >= 8.0) { - return R300_TX_MAX_ANISO_8_TO_1; - } else if (anisotropy >= 4.0) { - return R300_TX_MAX_ANISO_4_TO_1; - } else if (anisotropy >= 2.0) { - return R300_TX_MAX_ANISO_2_TO_1; - } else { - return R300_TX_MAX_ANISO_1_TO_1; - } -} - -/** - * Set the texture magnification and minification modes. - * - * \param t Texture whose filter modes are to be set - * \param minf Texture minification mode - * \param magf Texture magnification mode - * \param anisotropy Maximum anisotropy level - */ -static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) -{ - /* Force revalidation to account for switches from/to mipmapping. */ - t->validated = GL_FALSE; - - t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK); - t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY; - - /* Note that EXT_texture_filter_anisotropic is extremely vague about - * how anisotropic filtering interacts with the "normal" filter modes. - * When anisotropic filtering is enabled, we override min and mag - * filter settings completely. This includes driconf's settings. - */ - if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) { - t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO - | R300_TX_MIN_FILTER_ANISO - | R300_TX_MIN_FILTER_MIP_LINEAR - | aniso_filter(anisotropy); - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); - return; - } - - switch (minf) { - case GL_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST; - break; - case GL_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR; - break; - case GL_NEAREST_MIPMAP_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST; - break; - case GL_NEAREST_MIPMAP_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR; - break; - case GL_LINEAR_MIPMAP_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST; - break; - case GL_LINEAR_MIPMAP_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR; - break; - } - - /* Note we don't have 3D mipmaps so only use the mag filter setting - * to set the 3D texture filter mode. - */ - switch (magf) { - case GL_NEAREST: - t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST; - break; - case GL_LINEAR: - t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR; - break; - } -} - -static void r300SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4]) -{ - GLubyte c[4]; - CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); - t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); -} - -/** - * Changes variables and flags for a state update, which will happen at the - * next UpdateTextureState - */ - -static void r300TexParameter(struct gl_context * ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat * params) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - GLenum texBaseFormat; - - if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) { - fprintf(stderr, "%s( %s )\n", __FUNCTION__, - _mesa_lookup_enum_by_nr(pname)); - } - - switch (pname) { - case GL_TEXTURE_MIN_FILTER: - case GL_TEXTURE_MAG_FILTER: - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - r300SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy); - break; - - case GL_TEXTURE_WRAP_S: - case GL_TEXTURE_WRAP_T: - case GL_TEXTURE_WRAP_R: - r300UpdateTexWrap(t); - break; - - case GL_TEXTURE_BORDER_COLOR: - r300SetTexBorderColor(t, texObj->Sampler.BorderColor.f); - break; - - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - t->validated = GL_FALSE; - break; - - case GL_DEPTH_TEXTURE_MODE: - if (!texObj->Image[0][texObj->BaseLevel]) - return; - texBaseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat; - - if (texBaseFormat == GL_DEPTH_COMPONENT || - texBaseFormat == GL_DEPTH_STENCIL) { - r300SetDepthTexMode(texObj); - break; - } else { - /* If the texture isn't a depth texture, changing this - * state won't cause any changes to the hardware. - * Don't force a flush of texture state. - */ - return; - } - - default: - return; - } -} - -static void r300DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeonTexObj* t = radeon_tex_obj(texObj); - - if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, - (void *)texObj, - _mesa_lookup_enum_by_nr(texObj->Target)); - } - - if (rmesa) { - int i; - struct radeon_bo *bo; - bo = !t->mt ? t->bo : t->mt->bo; - if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->radeon.cmdbuf.cs)) { - radeon_firevertices(&rmesa->radeon); - } - - for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i) - if (rmesa->hw.textures[i] == t) - rmesa->hw.textures[i] = 0; - } - - if (t->bo) { - radeon_bo_unref(t->bo); - t->bo = NULL; - } - - radeon_miptree_unreference(&t->mt); - - _mesa_delete_texture_object(ctx, texObj); -} - -/** - * Allocate a new texture object. - * Called via ctx->Driver.NewTextureObject. - * Note: this function will be called during context creation to - * allocate the default texture objects. - * Fixup MaxAnisotropy according to user preference. - */ -static struct gl_texture_object *r300NewTextureObject(struct gl_context * ctx, - GLuint name, - GLenum target) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); - - - if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, - t, _mesa_lookup_enum_by_nr(target)); - } - - _mesa_initialize_texture_object(&t->base, name, target); - t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; - - /* Initialize hardware state */ - r300UpdateTexWrap(t); - r300SetTexFilter(t, t->base.Sampler.MinFilter, - t->base.Sampler.MagFilter, - t->base.Sampler.MaxAnisotropy); - r300SetTexBorderColor(t, t->base.Sampler.BorderColor.f); - - return &t->base; -} - -unsigned r300IsFormatRenderable(gl_format mesa_format) -{ - switch (mesa_format) - { - case MESA_FORMAT_RGB565: - case MESA_FORMAT_RGBA5551: - case MESA_FORMAT_RGBA8888: - case MESA_FORMAT_RGB565_REV: - case MESA_FORMAT_RGBA8888_REV: - case MESA_FORMAT_ARGB4444: - case MESA_FORMAT_ARGB1555: - case MESA_FORMAT_XRGB8888: - case MESA_FORMAT_ARGB8888: - case MESA_FORMAT_ARGB4444_REV: - case MESA_FORMAT_ARGB1555_REV: - case MESA_FORMAT_XRGB8888_REV: - case MESA_FORMAT_ARGB8888_REV: - case MESA_FORMAT_SRGBA8: - case MESA_FORMAT_SARGB8: - case MESA_FORMAT_SL8: - case MESA_FORMAT_A8: - case MESA_FORMAT_L8: - case MESA_FORMAT_I8: - case MESA_FORMAT_Z16: - return 1; - default: - return 0; - } -} - -unsigned r500IsFormatRenderable(gl_format mesa_format) -{ - if (mesa_format == MESA_FORMAT_S8_Z24) { - return 1; - } else { - return r300IsFormatRenderable(mesa_format); - } -} - -void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions) -{ - /* Note: we only plug in the functions we implement in the driver - * since _mesa_init_driver_functions() was already called. - */ - - radeon_init_common_texture_funcs(radeon, functions); - - functions->NewTextureObject = r300NewTextureObject; - functions->DeleteTexture = r300DeleteTexture; - functions->IsTextureResident = driIsTextureResident; - - functions->TexParameter = r300TexParameter; - -#if FEATURE_OES_EGL_image - functions->EGLImageTargetTexture2D = radeon_image_target_texture_2d; -#endif -} diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h deleted file mode 100644 index c44a39cb460..00000000000 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ /dev/null @@ -1,59 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <[email protected]> - */ - -#ifndef __r300_TEX_H__ -#define __r300_TEX_H__ - -extern void r300SetDepthTexMode(struct gl_texture_object *tObj); - -extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, - __DRIdrawable *dPriv); - -extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - GLint format, __DRIdrawable *dPriv); - -extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, - GLuint pitch); - -extern GLboolean r300ValidateBuffers(struct gl_context * ctx); - -extern void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions); - -int32_t r300TranslateTexFormat(gl_format mesaFormat); - -unsigned r300IsFormatRenderable(gl_format mesaFormat); -unsigned r500IsFormatRenderable(gl_format mesaFormat); - -#endif /* __r300_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c deleted file mode 100644 index 26ab0e5bf80..00000000000 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ /dev/null @@ -1,528 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Keith Whitwell <[email protected]> - * - * \todo Enable R300 texture tiling code? - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/macros.h" -#include "main/teximage.h" -#include "main/texobj.h" -#include "main/enums.h" -#include "main/simple_list.h" - -#include "r300_context.h" -#include "radeon_mipmap_tree.h" -#include "r300_tex.h" -#include "r300_reg.h" - -/* - * Note that the _REV formats are the same as the non-REV formats. This is - * because the REV and non-REV formats are identical as a byte string, but - * differ when accessed as 16-bit or 32-bit words depending on the endianness of - * the host. Since the textures are transferred to the R300 as a byte string - * (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats - * identically. -- paulus - */ - -int32_t r300TranslateTexFormat(gl_format mesaFormat) -{ - switch (mesaFormat) - { -#ifdef MESA_LITTLE_ENDIAN - case MESA_FORMAT_RGBA8888: - return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8); - case MESA_FORMAT_RGBA8888_REV: - return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8); - case MESA_FORMAT_ARGB8888: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); - case MESA_FORMAT_ARGB8888_REV: - return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8); -#else - case MESA_FORMAT_RGBA8888: - return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8); - case MESA_FORMAT_RGBA8888_REV: - return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8); - case MESA_FORMAT_ARGB8888: - return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8); - case MESA_FORMAT_ARGB8888_REV: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); -#endif - case MESA_FORMAT_XRGB8888: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - case MESA_FORMAT_RGB888: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - case MESA_FORMAT_RGB565: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - case MESA_FORMAT_RGB565_REV: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - case MESA_FORMAT_ARGB4444: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4); - case MESA_FORMAT_ARGB4444_REV: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4); - case MESA_FORMAT_ARGB1555: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5); - case MESA_FORMAT_ARGB1555_REV: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5); - case MESA_FORMAT_AL88: - return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8); - case MESA_FORMAT_AL88_REV: - return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8); - case MESA_FORMAT_RGB332: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2); - case MESA_FORMAT_A8: - return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8); - case MESA_FORMAT_L8: - return R300_EASY_TX_FORMAT(X, X, X, ONE, X8); - case MESA_FORMAT_I8: - return R300_EASY_TX_FORMAT(X, X, X, X, X8); - case MESA_FORMAT_YCBCR: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE; - case MESA_FORMAT_YCBCR_REV: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE; - case MESA_FORMAT_RGB_DXT1: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1); - case MESA_FORMAT_RGBA_DXT1: - return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1); - case MESA_FORMAT_RGBA_DXT3: - return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3); - case MESA_FORMAT_RGBA_DXT5: - return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5); - case MESA_FORMAT_RGBA_FLOAT32: - return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32); - case MESA_FORMAT_RGBA_FLOAT16: - return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16); - case MESA_FORMAT_ALPHA_FLOAT32: - return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32); - case MESA_FORMAT_ALPHA_FLOAT16: - return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16); - case MESA_FORMAT_LUMINANCE_FLOAT32: - return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32); - case MESA_FORMAT_LUMINANCE_FLOAT16: - return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16); - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: - return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32); - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: - return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16); - case MESA_FORMAT_INTENSITY_FLOAT32: - return R300_EASY_TX_FORMAT(X, X, X, X, FL_I32); - case MESA_FORMAT_INTENSITY_FLOAT16: - return R300_EASY_TX_FORMAT(X, X, X, X, FL_I16); - case MESA_FORMAT_Z16: - return R300_EASY_TX_FORMAT(X, X, X, X, X16); - case MESA_FORMAT_Z24_S8: - return R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8); - case MESA_FORMAT_S8_Z24: - return R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8); - case MESA_FORMAT_Z32: - return R300_EASY_TX_FORMAT(X, X, X, X, X32); - /* EXT_texture_sRGB */ - case MESA_FORMAT_SARGB8: - return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SLA8: - return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SL8: - return R300_EASY_TX_FORMAT(X, X, X, ONE, X8) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SRGB_DXT1: - return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SRGBA_DXT1: - return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SRGBA_DXT3: - return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3) | R300_TX_FORMAT_GAMMA; - case MESA_FORMAT_SRGBA_DXT5: - return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5) | R300_TX_FORMAT_GAMMA; - default: - return -1; - } -}; - -void r300SetDepthTexMode(struct gl_texture_object *tObj) -{ - static const GLuint formats[3][3] = { - { - R300_EASY_TX_FORMAT(X, X, X, ONE, X16), - R300_EASY_TX_FORMAT(X, X, X, X, X16), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16), - }, - { - R300_EASY_TX_FORMAT(Y, Y, Y, ONE, X24_Y8), - R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, Y, X24_Y8), - }, - { - R300_EASY_TX_FORMAT(X, X, X, ONE, X32), - R300_EASY_TX_FORMAT(X, X, X, X, X32), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32), - }, - }; - const GLuint *format; - radeonTexObjPtr t; - - if (!tObj) - return; - - t = radeon_tex_obj(tObj); - - switch (tObj->Image[0][tObj->BaseLevel]->TexFormat) { - case MESA_FORMAT_Z16: - format = formats[0]; - break; - case MESA_FORMAT_S8_Z24: - format = formats[1]; - break; - case MESA_FORMAT_Z32: - format = formats[2]; - break; - default: - /* Error...which should have already been caught by higher - * levels of Mesa. - */ - ASSERT(0); - return; - } - - switch (tObj->Sampler.DepthMode) { - case GL_LUMINANCE: - t->pp_txformat = format[0]; - break; - case GL_INTENSITY: - t->pp_txformat = format[1]; - break; - case GL_ALPHA: - t->pp_txformat = format[2]; - break; - default: - /* Error...which should have already been caught by higher - * levels of Mesa. - */ - ASSERT(0); - return; - } -} - - -/** - * Compute the cached hardware register values for the given texture object. - * - * \param rmesa Context pointer - * \param t the r300 texture object - */ -static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) -{ - const struct gl_texture_image *firstImage; - firstImage = t->base.Image[0][t->minLod]; - - if (!t->image_override) { - if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { - r300SetDepthTexMode(&t->base); - } else { - int32_t txformat = r300TranslateTexFormat(firstImage->TexFormat); - if (txformat < 0) { - _mesa_problem(rmesa->radeon.glCtx, "%s: Invalid format %s", - __FUNCTION__, _mesa_get_format_name(firstImage->TexFormat)); - exit(1); - } - t->pp_txformat = (uint32_t) txformat; - } - } - - if (t->image_override && t->bo) - return; - - t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT))) - | ((R300_TX_HEIGHTMASK_MASK & ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT))) - | ((R300_TX_DEPTHMASK_MASK & ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT))) - | ((R300_TX_MAX_MIP_LEVEL_MASK & ((t->maxLod - t->minLod) << R300_TX_MAX_MIP_LEVEL_SHIFT)))); - - t->tile_bits = 0; - - if (t->base.Target == GL_TEXTURE_CUBE_MAP) - t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; - if (t->base.Target == GL_TEXTURE_3D) - t->pp_txformat |= R300_TX_FORMAT_3D; - - - if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { - unsigned int align = (64 / _mesa_get_format_bytes(firstImage->TexFormat)) - 1; - t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; - if (!t->image_override) - t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1; - } - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (firstImage->Width > 2048) - t->pp_txpitch |= R500_TXWIDTH_BIT11; - else - t->pp_txpitch &= ~R500_TXWIDTH_BIT11; - if (firstImage->Height > 2048) - t->pp_txpitch |= R500_TXHEIGHT_BIT11; - else - t->pp_txpitch &= ~R500_TXHEIGHT_BIT11; - } -} - -/** - * Ensure the given texture is ready for rendering. - * - * Mostly this means populating the texture object's mipmap tree. - */ -static GLboolean r300_validate_texture(struct gl_context * ctx, struct gl_texture_object *texObj) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - radeonTexObj *t = radeon_tex_obj(texObj); - - if (!radeon_validate_texture_miptree(ctx, texObj)) - return GL_FALSE; - - /* Configure the hardware registers (more precisely, the cached version - * of the hardware registers). */ - setup_hardware_state(rmesa, t); - - t->validated = GL_TRUE; - return GL_TRUE; -} - -/** - * Ensure all enabled and complete textures are uploaded along with any buffers being used. - */ -GLboolean r300ValidateBuffers(struct gl_context * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct radeon_renderbuffer *rrb; - int i; - int ret; - - radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs); - - rrb = radeon_get_colorbuffer(&rmesa->radeon); - /* color buffer */ - if (rrb && rrb->bo) { - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, - rrb->bo, 0, - RADEON_GEM_DOMAIN_VRAM); - } - - /* depth buffer */ - rrb = radeon_get_depthbuffer(&rmesa->radeon); - if (rrb && rrb->bo) { - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, - rrb->bo, 0, - RADEON_GEM_DOMAIN_VRAM); - } - - for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { - radeonTexObj *t; - - if (!ctx->Texture.Unit[i]._ReallyEnabled) - continue; - - if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { - _mesa_warning(ctx, - "failed to validate texture for unit %d.\n", - i); - } - t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); - if (t->image_override && t->bo) - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, - t->bo, - RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - else if (t->mt->bo) - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, - t->mt->bo, - RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - } - - ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0); - if (ret) - return GL_FALSE; - return GL_TRUE; -} - -void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, - unsigned long long offset, GLint depth, GLuint pitch) -{ - r300ContextPtr rmesa = pDRICtx->driverPrivate; - struct gl_texture_object *tObj = - _mesa_lookup_texture(rmesa->radeon.glCtx, texname); - radeonTexObjPtr t = radeon_tex_obj(tObj); - uint32_t pitch_val; - - if (!tObj) - return; - - t->image_override = GL_TRUE; - - if (!offset) - return; - - t->bo = NULL; - t->override_offset = offset; - t->pp_txpitch &= (1 << 13) -1; - pitch_val = pitch; - - switch (depth) { - case 32: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); - pitch_val /= 4; - break; - case 24: - default: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - pitch_val /= 4; - break; - case 16: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - pitch_val /= 2; - break; - } - pitch_val--; - - t->pp_txpitch |= pitch_val; -} - -void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, __DRIdrawable *dPriv) -{ - struct gl_texture_unit *texUnit; - struct gl_texture_object *texObj; - struct gl_texture_image *texImage; - struct radeon_renderbuffer *rb; - radeon_texture_image *rImage; - radeonContextPtr radeon; - r300ContextPtr rmesa; - struct radeon_framebuffer *rfb; - radeonTexObjPtr t; - uint32_t pitch_val; - gl_format texFormat; - - radeon = pDRICtx->driverPrivate; - rmesa = pDRICtx->driverPrivate; - - rfb = dPriv->driverPrivate; - texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; - texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); - texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); - - rImage = get_radeon_texture_image(texImage); - t = radeon_tex_obj(texObj); - if (t == NULL) { - return; - } - - radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); - rb = rfb->color_rb[0]; - if (rb->bo == NULL) { - /* Failed to BO for the buffer */ - return; - } - - _mesa_lock_texture(radeon->glCtx, texObj); - if (t->bo) { - radeon_bo_unref(t->bo); - t->bo = NULL; - } - if (rImage->bo) { - radeon_bo_unref(rImage->bo); - rImage->bo = NULL; - } - - radeon_miptree_unreference(&t->mt); - radeon_miptree_unreference(&rImage->mt); - - rImage->bo = rb->bo; - radeon_bo_ref(rImage->bo); - t->bo = rb->bo; - radeon_bo_ref(t->bo); - t->tile_bits = 0; - t->image_override = GL_TRUE; - t->override_offset = 0; - t->pp_txpitch &= (1 << 13) -1; - pitch_val = rb->pitch; - switch (rb->cpp) { - case 4: - if (texture_format == __DRI_TEXTURE_FORMAT_RGB) { - texFormat = MESA_FORMAT_RGB888; - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - } - else { - texFormat = MESA_FORMAT_ARGB8888; - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); - } - pitch_val /= 4; - break; - case 3: - default: - texFormat = MESA_FORMAT_RGB888; - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); - pitch_val /= 4; - break; - case 2: - texFormat = MESA_FORMAT_RGB565; - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); - pitch_val /= 2; - break; - } - - _mesa_init_teximage_fields(radeon->glCtx, target, texImage, - rb->base.Width, rb->base.Height, 1, 0, - rb->cpp, texFormat); - rImage->base.RowStride = rb->pitch / rb->cpp; - - - pitch_val--; - t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT))) - | ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT)))); - t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; - t->pp_txpitch |= pitch_val; - - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (rb->base.Width > 2048) - t->pp_txpitch |= R500_TXWIDTH_BIT11; - else - t->pp_txpitch &= ~R500_TXWIDTH_BIT11; - if (rb->base.Height > 2048) - t->pp_txpitch |= R500_TXHEIGHT_BIT11; - else - t->pp_txpitch &= ~R500_TXHEIGHT_BIT11; - } - t->validated = GL_TRUE; - _mesa_unlock_texture(radeon->glCtx, texObj); - return; -} - -void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) -{ - r300SetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv); -} diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c deleted file mode 100644 index eacc85d02e3..00000000000 --- a/src/mesa/drivers/dri/r300/r300_vertprog.c +++ /dev/null @@ -1,421 +0,0 @@ -/************************************************************************** - -Copyright (C) 2005 Aapo Tahkola <[email protected]> -Copyright (C) 2008 Oliver McFadden <[email protected]> - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* Radeon R5xx Acceleration, Revision 1.2 */ - -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" -#include "program/program.h" -#include "program/programopt.h" -#include "program/prog_instruction.h" -#include "program/prog_parameter.h" -#include "program/prog_print.h" -#include "program/prog_statevars.h" -#include "tnl/tnl.h" - -#include "compiler/radeon_compiler.h" -#include "radeon_mesa_to_rc.h" -#include "r300_context.h" -#include "r300_fragprog_common.h" -#include "r300_state.h" - -/** - * Write parameter array for the given vertex program into dst. - * Return the total number of components written. - */ -static int r300VertexProgUpdateParams(struct gl_context * ctx, struct r300_vertex_program *vp, float *dst) -{ - int i; - - if (vp->Base->IsNVProgram) { - _mesa_load_tracked_matrices(ctx); - } else { - if (vp->Base->Base.Parameters) { - _mesa_load_state_parameters(ctx, vp->Base->Base.Parameters); - } - } - - for(i = 0; i < vp->code.constants.Count; ++i) { - const float * src = 0; - const struct rc_constant * constant = &vp->code.constants.Constants[i]; - - switch(constant->Type) { - case RC_CONSTANT_EXTERNAL: - if (vp->Base->IsNVProgram) { - src = ctx->VertexProgram.Parameters[constant->u.External]; - } else { - src = &vp->Base->Base.Parameters->ParameterValues[constant->u.External][0].f; - } - break; - - case RC_CONSTANT_IMMEDIATE: - src = constant->u.Immediate; - break; - } - - assert(src); - dst[4*i] = src[0]; - dst[4*i + 1] = src[1]; - dst[4*i + 2] = src[2]; - dst[4*i + 3] = src[3]; - } - - return 4 * vp->code.constants.Count; -} - -static GLbitfield compute_required_outputs(struct gl_vertex_program * vp, GLbitfield fpreads) -{ - GLbitfield outputs = 0; - int i; - -#define ADD_OUTPUT(fp_attr, vp_result) \ - do { \ - if (fpreads & (1 << (fp_attr))) \ - outputs |= (1 << (vp_result)); \ - } while (0) - - ADD_OUTPUT(FRAG_ATTRIB_COL0, VERT_RESULT_COL0); - ADD_OUTPUT(FRAG_ATTRIB_COL1, VERT_RESULT_COL1); - - for (i = 0; i <= 7; ++i) { - ADD_OUTPUT(FRAG_ATTRIB_TEX0 + i, VERT_RESULT_TEX0 + i); - } - -#undef ADD_OUTPUT - - if ((fpreads & (1 << FRAG_ATTRIB_COL0)) && - (vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC0))) - outputs |= 1 << VERT_RESULT_BFC0; - if ((fpreads & (1 << FRAG_ATTRIB_COL1)) && - (vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC1))) - outputs |= 1 << VERT_RESULT_BFC1; - - outputs |= 1 << VERT_RESULT_HPOS; - if (vp->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ)) - outputs |= 1 << VERT_RESULT_PSIZ; - - return outputs; -} - - -static void t_inputs_outputs(struct r300_vertex_program_compiler * c) -{ - int i; - int cur_reg; - GLuint OutputsWritten, InputsRead; - - OutputsWritten = c->Base.Program.OutputsWritten; - InputsRead = c->Base.Program.InputsRead; - - cur_reg = -1; - for (i = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) - c->code->inputs[i] = ++cur_reg; - else - c->code->inputs[i] = -1; - } - - cur_reg = 0; - for (i = 0; i < VERT_RESULT_MAX; i++) - c->code->outputs[i] = -1; - - assert(OutputsWritten & (1 << VERT_RESULT_HPOS)); - - if (OutputsWritten & (1 << VERT_RESULT_HPOS)) { - c->code->outputs[VERT_RESULT_HPOS] = cur_reg++; - } - - if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) { - c->code->outputs[VERT_RESULT_PSIZ] = cur_reg++; - } - - /* If we're writing back facing colors we need to send - * four colors to make front/back face colors selection work. - * If the vertex program doesn't write all 4 colors, lets - * pretend it does by skipping output index reg so the colors - * get written into appropriate output vectors. - */ - if (OutputsWritten & (1 << VERT_RESULT_COL0)) { - c->code->outputs[VERT_RESULT_COL0] = cur_reg++; - } else if (OutputsWritten & (1 << VERT_RESULT_BFC0) || - OutputsWritten & (1 << VERT_RESULT_BFC1)) { - cur_reg++; - } - - if (OutputsWritten & (1 << VERT_RESULT_COL1)) { - c->code->outputs[VERT_RESULT_COL1] = cur_reg++; - } else if (OutputsWritten & (1 << VERT_RESULT_BFC0) || - OutputsWritten & (1 << VERT_RESULT_BFC1)) { - cur_reg++; - } - - if (OutputsWritten & (1 << VERT_RESULT_BFC0)) { - c->code->outputs[VERT_RESULT_BFC0] = cur_reg++; - } else if (OutputsWritten & (1 << VERT_RESULT_BFC1)) { - cur_reg++; - } - - if (OutputsWritten & (1 << VERT_RESULT_BFC1)) { - c->code->outputs[VERT_RESULT_BFC1] = cur_reg++; - } else if (OutputsWritten & (1 << VERT_RESULT_BFC0)) { - cur_reg++; - } - - for (i = VERT_RESULT_TEX0; i <= VERT_RESULT_TEX7; i++) { - if (OutputsWritten & (1 << i)) { - c->code->outputs[i] = cur_reg++; - } - } - - if (OutputsWritten & (1 << VERT_RESULT_FOGC)) { - c->code->outputs[VERT_RESULT_FOGC] = cur_reg++; - } -} - -/** - * The NV_vertex_program spec mandates that all registers be - * initialized to zero. We do this here unconditionally. - * - * \note We rely on dead-code elimination in the compiler. - */ -static void initialize_NV_registers(struct radeon_compiler * compiler) -{ - unsigned int reg; - struct rc_instruction * inst; - - for(reg = 0; reg < 12; ++reg) { - inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions); - inst->U.I.Opcode = RC_OPCODE_MOV; - inst->U.I.DstReg.File = RC_FILE_TEMPORARY; - inst->U.I.DstReg.Index = reg; - inst->U.I.SrcReg[0].File = RC_FILE_NONE; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; - } - - inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions); - inst->U.I.Opcode = RC_OPCODE_ARL; - inst->U.I.DstReg.File = RC_FILE_ADDRESS; - inst->U.I.DstReg.Index = 0; - inst->U.I.DstReg.WriteMask = WRITEMASK_X; - inst->U.I.SrcReg[0].File = RC_FILE_NONE; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; -} - -static struct r300_vertex_program *build_program(struct gl_context *ctx, - struct r300_vertex_program_key *wanted_key, - const struct gl_vertex_program *mesa_vp) -{ - struct r300_vertex_program *vp; - struct r300_vertex_program_compiler compiler; - - vp = calloc(1, sizeof(*vp)); - vp->Base = _mesa_clone_vertex_program(ctx, mesa_vp); - memcpy(&vp->key, wanted_key, sizeof(vp->key)); - - memset(&compiler, 0, sizeof(compiler)); - rc_init(&compiler.Base); - compiler.Base.Debug = (RADEON_DEBUG & RADEON_VERTS) ? GL_TRUE : GL_FALSE; - - compiler.code = &vp->code; - compiler.RequiredOutputs = compute_required_outputs(vp->Base, vp->key.FpReads); - compiler.SetHwInputOutput = &t_inputs_outputs; - compiler.Base.is_r500 = R300_CONTEXT(ctx)->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515; - compiler.Base.disable_optimizations = 0; - compiler.Base.has_half_swizzles = 0; - compiler.Base.max_temp_regs = 32; - compiler.Base.max_constants = 256; - compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256; - - if (compiler.Base.Debug) { - fprintf(stderr, "Initial vertex program:\n"); - _mesa_print_program(&vp->Base->Base); - fflush(stderr); - } - - if (mesa_vp->IsPositionInvariant) { - _mesa_insert_mvp_code(ctx, vp->Base); - } - - radeon_mesa_to_rc_program(&compiler.Base, &vp->Base->Base); - - if (mesa_vp->IsNVProgram) - initialize_NV_registers(&compiler.Base); - - rc_move_output(&compiler.Base, VERT_RESULT_PSIZ, VERT_RESULT_PSIZ, WRITEMASK_X); - - if (vp->key.WPosAttr != FRAG_ATTRIB_MAX) { - unsigned int vp_wpos_attr = vp->key.WPosAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0; - - /* Set empty writemask for instructions writing to vp_wpos_attr - * before moving the wpos attr there. - * Such instructions will be removed by DCE. - */ - rc_move_output(&compiler.Base, vp_wpos_attr, vp->key.WPosAttr, 0); - rc_copy_output(&compiler.Base, VERT_RESULT_HPOS, vp_wpos_attr); - } - - if (vp->key.FogAttr != FRAG_ATTRIB_MAX) { - unsigned int vp_fog_attr = vp->key.FogAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0; - - /* Set empty writemask for instructions writing to vp_fog_attr - * before moving the fog attr there. - * Such instructions will be removed by DCE. - */ - rc_move_output(&compiler.Base, vp_fog_attr, vp->key.FogAttr, 0); - rc_move_output(&compiler.Base, VERT_RESULT_FOGC, vp_fog_attr, WRITEMASK_X); - } - - r3xx_compile_vertex_program(&compiler); - - if (vp->code.constants.Count > ctx->Const.VertexProgram.MaxParameters) { - rc_error(&compiler.Base, "Program exceeds constant buffer size limit\n"); - } - - vp->error = compiler.Base.Error; - - vp->Base->Base.InputsRead = vp->code.InputsRead; - vp->Base->Base.OutputsWritten = vp->code.OutputsWritten; - - rc_destroy(&compiler.Base); - - return vp; -} - -struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx) -{ - r300ContextPtr r300 = R300_CONTEXT(ctx); - struct r300_vertex_program_key wanted_key = { 0 }; - struct r300_vertex_program_cont *vpc; - struct r300_vertex_program *vp; - - vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current; - - if (!r300->selected_fp) { - /* This can happen when GetProgramiv is called to check - * whether the program runs natively. - * - * To be honest, this is not a very good solution, - * but solving the problem of reporting good values - * for those queries is tough anyway considering that - * we recompile vertex programs based on the precise - * fragment program that is in use. - */ - r300SelectAndTranslateFragmentShader(ctx); - } - - assert(r300->selected_fp); - wanted_key.FpReads = r300->selected_fp->InputsRead; - wanted_key.FogAttr = r300->selected_fp->fog_attr; - wanted_key.WPosAttr = r300->selected_fp->wpos_attr; - - for (vp = vpc->progs; vp; vp = vp->next) { - if (memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) { - return r300->selected_vp = vp; - } - } - - vp = build_program(ctx, &wanted_key, &vpc->mesa_program); - vp->next = vpc->progs; - vpc->progs = vp; - - return r300->selected_vp = vp; -} - -#define bump_vpu_count(ptr, new_count) do { \ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \ - int _nc=(new_count)/4; \ - if(_nc>_p->vpu.count)_p->vpu.count=_nc; \ - } while(0) - -static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_vertex_program_code *code) -{ - int i; - - assert((code->length > 0) && (code->length % 4 == 0)); - - switch ((dest >> 8) & 0xf) { - case 0: - R300_STATECHANGE(r300, vpi); - for (i = 0; i < code->length; i++) - r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]); - bump_vpu_count(r300->hw.vpi.cmd, code->length + 4 * (dest & 0xff)); - break; - case 2: - R300_STATECHANGE(r300, vpp); - for (i = 0; i < code->length; i++) - r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]); - bump_vpu_count(r300->hw.vpp.cmd, code->length + 4 * (dest & 0xff)); - break; - case 4: - R300_STATECHANGE(r300, vps); - for (i = 0; i < code->length; i++) - r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (code->body.d[i]); - bump_vpu_count(r300->hw.vps.cmd, code->length + 4 * (dest & 0xff)); - break; - default: - fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest); - exit(-1); - } -} - -void r300SetupVertexProgram(r300ContextPtr rmesa) -{ - struct gl_context *ctx = rmesa->radeon.glCtx; - struct r300_vertex_program *prog = rmesa->selected_vp; - int inst_count = 0; - int param_count = 0; - - /* Reset state, in case we don't use something */ - ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0; - - R300_STATECHANGE(rmesa, vap_cntl); - R300_STATECHANGE(rmesa, vpp); - param_count = r300VertexProgUpdateParams(ctx, prog, (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]); - if (!rmesa->radeon.radeonScreen->kernel_mm && param_count > 255 * 4) { - WARN_ONCE("Too many VP params, expect rendering errors\n"); - } - /* Prevent the overflow (vpu.count is u8) */ - bump_vpu_count(rmesa->hw.vpp.cmd, MIN2(255 * 4, param_count)); - param_count /= 4; - - r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, &(prog->code)); - inst_count = (prog->code.length / 4) - 1; - - r300VapCntl(rmesa, _mesa_bitcount(prog->code.InputsRead), - _mesa_bitcount(prog->code.OutputsWritten), prog->code.num_temporaries); - - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | ((param_count - 1) << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); -} diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h deleted file mode 100644 index ce24dcb3535..00000000000 --- a/src/mesa/drivers/dri/r300/r300_vertprog.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __R300_VERTPROG_H_ -#define __R300_VERTPROG_H_ - -#include "r300_reg.h" - - -void r300SetupVertexProgram(r300ContextPtr rmesa); - -struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx); - -#endif diff --git a/src/mesa/drivers/dri/r300/radeon_bo.c b/src/mesa/drivers/dri/r300/radeon_bo.c deleted file mode 120000 index 9448ffee54b..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_bo.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_bo.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_bo_int_drm.h b/src/mesa/drivers/dri/r300/radeon_bo_int_drm.h deleted file mode 120000 index 029450928be..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_bo_int_drm.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_bo_int_drm.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_bo_legacy.c b/src/mesa/drivers/dri/r300/radeon_bo_legacy.c deleted file mode 120000 index 79ad050e6b6..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_bo_legacy.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_bo_legacy.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_bo_legacy.h b/src/mesa/drivers/dri/r300/radeon_bo_legacy.h deleted file mode 120000 index 83b0f7ffabe..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_bo_legacy.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_bo_legacy.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/r300/radeon_bocs_wrapper.h deleted file mode 120000 index ca894b2443c..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_bocs_wrapper.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_bocs_wrapper.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_buffer_objects.c b/src/mesa/drivers/dri/r300/radeon_buffer_objects.c deleted file mode 120000 index f6a5f664701..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_buffer_objects.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_buffer_objects.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_buffer_objects.h b/src/mesa/drivers/dri/r300/radeon_buffer_objects.h deleted file mode 120000 index 2f134fd17b8..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_buffer_objects.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_buffer_objects.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_chipset.h b/src/mesa/drivers/dri/r300/radeon_chipset.h deleted file mode 120000 index eba99001ff8..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_chipset.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_chipset.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_cmdbuf.h b/src/mesa/drivers/dri/r300/radeon_cmdbuf.h deleted file mode 120000 index a799e1dc6df..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cmdbuf.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cmdbuf.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_common.c b/src/mesa/drivers/dri/r300/radeon_common.c deleted file mode 120000 index 67b19ba940d..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_common.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_common.h b/src/mesa/drivers/dri/r300/radeon_common.h deleted file mode 120000 index 5bcb696a9f7..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_common.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_common_context.c b/src/mesa/drivers/dri/r300/radeon_common_context.c deleted file mode 120000 index 86800f3819c..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_common_context.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common_context.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_common_context.h b/src/mesa/drivers/dri/r300/radeon_common_context.h deleted file mode 120000 index 4d663125500..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_common_context.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common_context.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h deleted file mode 100644 index 52b7fb91e65..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ /dev/null @@ -1,60 +0,0 @@ -/************************************************************************** - -Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and - VA Linux Systems Inc., Fremont, California. -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Gareth Hughes <[email protected]> - * Keith Whitwell <[email protected]> - * Kevin E. Martin <[email protected]> - * Nicolai Haehnle <[email protected]> - */ - -#ifndef __RADEON_CONTEXT_H__ -#define __RADEON_CONTEXT_H__ - -#include "main/mtypes.h" -#include "main/colormac.h" -#include "radeon_screen.h" -#include "drm.h" -#include "dri_util.h" - -#define FALLBACK( radeon, bit, mode ) fprintf(stderr, "%s:%s\n", __LINE__, __FILE__); - -/* TCL fallbacks */ -extern void radeonTclFallback(struct gl_context * ctx, GLuint bit, GLboolean mode); - -#define TCL_FALLBACK( ctx, bit, mode ) ; - - -#endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_cs.c b/src/mesa/drivers/dri/r300/radeon_cs.c deleted file mode 120000 index 66b7ad1eb03..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cs.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cs.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_cs_int_drm.h b/src/mesa/drivers/dri/r300/radeon_cs_int_drm.h deleted file mode 120000 index 462f5245d0e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cs_int_drm.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cs_int_drm.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_cs_legacy.c b/src/mesa/drivers/dri/r300/radeon_cs_legacy.c deleted file mode 120000 index 006720f8a46..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cs_legacy.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cs_legacy.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_cs_legacy.h b/src/mesa/drivers/dri/r300/radeon_cs_legacy.h deleted file mode 120000 index a5f95e0a3dc..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cs_legacy.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cs_legacy.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_cs_space_drm.c b/src/mesa/drivers/dri/r300/radeon_cs_space_drm.c deleted file mode 120000 index c248ea7d1a5..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_cs_space_drm.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cs_space_drm.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_debug.c b/src/mesa/drivers/dri/r300/radeon_debug.c deleted file mode 120000 index c98c2e074c5..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_debug.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_debug.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_debug.h b/src/mesa/drivers/dri/r300/radeon_debug.h deleted file mode 120000 index bd8aa28e89e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_debug.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_debug.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_dma.c b/src/mesa/drivers/dri/r300/radeon_dma.c deleted file mode 120000 index 43be0006255..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_dma.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_dma.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_dma.h b/src/mesa/drivers/dri/r300/radeon_dma.h deleted file mode 120000 index 82e50634e3c..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_dma.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_dma.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_fbo.c b/src/mesa/drivers/dri/r300/radeon_fbo.c deleted file mode 120000 index 0d738d8d780..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_fbo.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_fbo.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c deleted file mode 120000 index af4108a8e30..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_lock.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h deleted file mode 120000 index 64bdf94ee7e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_lock.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c deleted file mode 100644 index b1dfccd22d0..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2009 Nicolai Haehnle. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "radeon_mesa_to_rc.h" - -#include "main/mtypes.h" -#include "program/prog_instruction.h" -#include "program/prog_parameter.h" - -#include "compiler/radeon_compiler.h" -#include "compiler/radeon_program.h" - - -static rc_opcode translate_opcode(gl_inst_opcode opcode) -{ - switch(opcode) { - case OPCODE_NOP: return RC_OPCODE_NOP; - case OPCODE_ABS: return RC_OPCODE_ABS; - case OPCODE_ADD: return RC_OPCODE_ADD; - case OPCODE_ARL: return RC_OPCODE_ARL; - case OPCODE_CMP: return RC_OPCODE_CMP; - case OPCODE_COS: return RC_OPCODE_COS; - case OPCODE_DDX: return RC_OPCODE_DDX; - case OPCODE_DDY: return RC_OPCODE_DDY; - case OPCODE_DP3: return RC_OPCODE_DP3; - case OPCODE_DP4: return RC_OPCODE_DP4; - case OPCODE_DPH: return RC_OPCODE_DPH; - case OPCODE_DST: return RC_OPCODE_DST; - case OPCODE_EX2: return RC_OPCODE_EX2; - case OPCODE_EXP: return RC_OPCODE_EXP; - case OPCODE_FLR: return RC_OPCODE_FLR; - case OPCODE_FRC: return RC_OPCODE_FRC; - case OPCODE_KIL: return RC_OPCODE_KIL; - case OPCODE_LG2: return RC_OPCODE_LG2; - case OPCODE_LIT: return RC_OPCODE_LIT; - case OPCODE_LOG: return RC_OPCODE_LOG; - case OPCODE_LRP: return RC_OPCODE_LRP; - case OPCODE_MAD: return RC_OPCODE_MAD; - case OPCODE_MAX: return RC_OPCODE_MAX; - case OPCODE_MIN: return RC_OPCODE_MIN; - case OPCODE_MOV: return RC_OPCODE_MOV; - case OPCODE_MUL: return RC_OPCODE_MUL; - case OPCODE_POW: return RC_OPCODE_POW; - case OPCODE_RCP: return RC_OPCODE_RCP; - case OPCODE_RSQ: return RC_OPCODE_RSQ; - case OPCODE_SCS: return RC_OPCODE_SCS; - case OPCODE_SEQ: return RC_OPCODE_SEQ; - case OPCODE_SFL: return RC_OPCODE_SFL; - case OPCODE_SGE: return RC_OPCODE_SGE; - case OPCODE_SGT: return RC_OPCODE_SGT; - case OPCODE_SIN: return RC_OPCODE_SIN; - case OPCODE_SLE: return RC_OPCODE_SLE; - case OPCODE_SLT: return RC_OPCODE_SLT; - case OPCODE_SNE: return RC_OPCODE_SNE; - case OPCODE_SUB: return RC_OPCODE_SUB; - case OPCODE_SWZ: return RC_OPCODE_SWZ; - case OPCODE_TEX: return RC_OPCODE_TEX; - case OPCODE_TXB: return RC_OPCODE_TXB; - case OPCODE_TXD: return RC_OPCODE_TXD; - case OPCODE_TXL: return RC_OPCODE_TXL; - case OPCODE_TXP: return RC_OPCODE_TXP; - case OPCODE_XPD: return RC_OPCODE_XPD; - default: return RC_OPCODE_ILLEGAL_OPCODE; - } -} - -static rc_saturate_mode translate_saturate(unsigned int saturate) -{ - switch(saturate) { - default: - case SATURATE_OFF: return RC_SATURATE_NONE; - case SATURATE_ZERO_ONE: return RC_SATURATE_ZERO_ONE; - } -} - -static rc_register_file translate_register_file(unsigned int file) -{ - switch(file) { - case PROGRAM_TEMPORARY: return RC_FILE_TEMPORARY; - case PROGRAM_INPUT: return RC_FILE_INPUT; - case PROGRAM_OUTPUT: return RC_FILE_OUTPUT; - case PROGRAM_LOCAL_PARAM: - case PROGRAM_ENV_PARAM: - case PROGRAM_STATE_VAR: - case PROGRAM_NAMED_PARAM: - case PROGRAM_CONSTANT: - case PROGRAM_UNIFORM: return RC_FILE_CONSTANT; - case PROGRAM_ADDRESS: return RC_FILE_ADDRESS; - default: return RC_FILE_NONE; - } -} - -static void translate_srcreg(struct rc_src_register * dest, struct prog_src_register * src) -{ - dest->File = translate_register_file(src->File); - dest->Index = src->Index; - dest->RelAddr = src->RelAddr; - dest->Swizzle = src->Swizzle; - dest->Abs = src->Abs; - dest->Negate = src->Negate; -} - -static void translate_dstreg(struct rc_dst_register * dest, struct prog_dst_register * src) -{ - dest->File = translate_register_file(src->File); - dest->Index = src->Index; - dest->WriteMask = src->WriteMask; -} - -static rc_texture_target translate_tex_target(gl_texture_index target) -{ - switch(target) { - case TEXTURE_2D_ARRAY_INDEX: return RC_TEXTURE_2D_ARRAY; - case TEXTURE_1D_ARRAY_INDEX: return RC_TEXTURE_1D_ARRAY; - case TEXTURE_CUBE_INDEX: return RC_TEXTURE_CUBE; - case TEXTURE_3D_INDEX: return RC_TEXTURE_3D; - case TEXTURE_RECT_INDEX: return RC_TEXTURE_RECT; - default: - case TEXTURE_2D_INDEX: return RC_TEXTURE_2D; - case TEXTURE_1D_INDEX: return RC_TEXTURE_1D; - } -} - -static void translate_instruction(struct radeon_compiler * c, - struct rc_instruction * dest, struct prog_instruction * src) -{ - const struct rc_opcode_info * opcode; - unsigned int i; - - dest->U.I.Opcode = translate_opcode(src->Opcode); - if (dest->U.I.Opcode == RC_OPCODE_ILLEGAL_OPCODE) { - rc_error(c, "Unsupported opcode %i\n", src->Opcode); - return; - } - dest->U.I.SaturateMode = translate_saturate(src->SaturateMode); - - opcode = rc_get_opcode_info(dest->U.I.Opcode); - - for(i = 0; i < opcode->NumSrcRegs; ++i) - translate_srcreg(&dest->U.I.SrcReg[i], &src->SrcReg[i]); - - if (opcode->HasDstReg) - translate_dstreg(&dest->U.I.DstReg, &src->DstReg); - - if (opcode->HasTexture) { - dest->U.I.TexSrcUnit = src->TexSrcUnit; - dest->U.I.TexSrcTarget = translate_tex_target(src->TexSrcTarget); - dest->U.I.TexShadow = src->TexShadow; - dest->U.I.TexSwizzle = RC_SWIZZLE_XYZW; - } -} - -void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program) -{ - struct prog_instruction *source; - unsigned int i; - - for(source = program->Instructions; source->Opcode != OPCODE_END; ++source) { - struct rc_instruction * dest = rc_insert_new_instruction(c, c->Program.Instructions.Prev); - translate_instruction(c, dest, source); - } - - c->Program.ShadowSamplers = program->ShadowSamplers; - c->Program.InputsRead = program->InputsRead; - c->Program.OutputsWritten = program->OutputsWritten; - - int isNVProgram = 0; - - if (program->Target == GL_VERTEX_PROGRAM_ARB) { - struct gl_vertex_program * vp = (struct gl_vertex_program *) program; - isNVProgram = vp->IsNVProgram; - } - - if (isNVProgram) { - /* NV_vertex_program has a fixed-sized constant environment. - * This could be handled more efficiently for programs that - * do not use relative addressing. - */ - for(i = 0; i < 96; ++i) { - struct rc_constant constant; - - constant.Type = RC_CONSTANT_EXTERNAL; - constant.Size = 4; - constant.u.External = i; - - rc_constants_add(&c->Program.Constants, &constant); - } - } else { - for(i = 0; i < program->Parameters->NumParameters; ++i) { - struct rc_constant constant; - - constant.Type = RC_CONSTANT_EXTERNAL; - constant.Size = 4; - constant.u.External = i; - - rc_constants_add(&c->Program.Constants, &constant); - } - } -} diff --git a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.h b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.h deleted file mode 100644 index 9511a04f36f..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2009 Nicolai Haehnle. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef RADEON_MESA_TO_RC_H -#define RADEON_MESA_TO_RC_H - -struct gl_program; -struct radeon_compiler; - -void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program); - -#endif /* RADEON_MESA_TO_RC_H */ diff --git a/src/mesa/drivers/dri/r300/radeon_mipmap_tree.c b/src/mesa/drivers/dri/r300/radeon_mipmap_tree.c deleted file mode 120000 index 31c0cfbe942..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_mipmap_tree.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_mipmap_tree.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_mipmap_tree.h b/src/mesa/drivers/dri/r300/radeon_mipmap_tree.h deleted file mode 120000 index 254d50cf8c5..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_mipmap_tree.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_mipmap_tree.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_pixel_read.c b/src/mesa/drivers/dri/r300/radeon_pixel_read.c deleted file mode 120000 index 3b03803126f..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_pixel_read.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_pixel_read.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_queryobj.c b/src/mesa/drivers/dri/r300/radeon_queryobj.c deleted file mode 120000 index 1d6ebc1c48b..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_queryobj.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_queryobj.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_queryobj.h b/src/mesa/drivers/dri/r300/radeon_queryobj.h deleted file mode 120000 index 8f6f842b0a6..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_queryobj.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_queryobj.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_screen.c b/src/mesa/drivers/dri/r300/radeon_screen.c deleted file mode 120000 index 86161118dd3..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_screen.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_screen.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_screen.h b/src/mesa/drivers/dri/r300/radeon_screen.h deleted file mode 120000 index 23bb6bd4598..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_screen.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_screen.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c deleted file mode 120000 index 232868c4c9e..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_span.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_span.h b/src/mesa/drivers/dri/r300/radeon_span.h deleted file mode 120000 index f9d634508c2..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_span.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_span.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_tex_copy.c b/src/mesa/drivers/dri/r300/radeon_tex_copy.c deleted file mode 120000 index dfa5ba34e65..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_tex_copy.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tex_copy.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_texture.c b/src/mesa/drivers/dri/r300/radeon_texture.c deleted file mode 120000 index a822710915f..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_texture.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_texture.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_texture.h b/src/mesa/drivers/dri/r300/radeon_texture.h deleted file mode 120000 index 17fac3d5ea5..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_texture.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_texture.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_tile.c b/src/mesa/drivers/dri/r300/radeon_tile.c deleted file mode 120000 index d4bfe27da64..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_tile.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tile.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_tile.h b/src/mesa/drivers/dri/r300/radeon_tile.h deleted file mode 120000 index 31074c581ea..00000000000 --- a/src/mesa/drivers/dri/r300/radeon_tile.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tile.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/server/radeon.h b/src/mesa/drivers/dri/r300/server/radeon.h deleted file mode 120000 index 81274a54f11..00000000000 --- a/src/mesa/drivers/dri/r300/server/radeon.h +++ /dev/null @@ -1 +0,0 @@ -../../radeon/server/radeon.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/server/radeon_dri.h b/src/mesa/drivers/dri/r300/server/radeon_dri.h deleted file mode 120000 index 27c591d3c9d..00000000000 --- a/src/mesa/drivers/dri/r300/server/radeon_dri.h +++ /dev/null @@ -1 +0,0 @@ -../../radeon/server/radeon_dri.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/server/radeon_macros.h b/src/mesa/drivers/dri/r300/server/radeon_macros.h deleted file mode 120000 index c56cd735b83..00000000000 --- a/src/mesa/drivers/dri/r300/server/radeon_macros.h +++ /dev/null @@ -1 +0,0 @@ -../../radeon/server/radeon_macros.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/server/radeon_reg.h b/src/mesa/drivers/dri/r300/server/radeon_reg.h deleted file mode 120000 index e2349dcb685..00000000000 --- a/src/mesa/drivers/dri/r300/server/radeon_reg.h +++ /dev/null @@ -1 +0,0 @@ -../../radeon/server/radeon_reg.h
\ No newline at end of file |