r200/r300: add aperture space checks

1 files changed, 51 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 68c7ca3d29f..7ffc15fe39d 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -49,6 +49,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_ioctl.h"
 #include "radeon_ioctl.h"
 #include "radeon_mipmap_tree.h"
+#include "radeon_cs.h"
 #include "r300_tex.h"
 #include "r300_reg.h"
 #include "radeon_buffer.h"
@@ -265,13 +266,43 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object
 
 
 /**
- * Ensure all enabled and complete textures are uploaded.
+ * Ensure all enabled and complete textures are uploaded along with any buffers being used.
  */
-void r300ValidateTextures(GLcontext * ctx)
+GLboolean r300ValidateBuffers(GLcontext * ctx)
 {
+	r300ContextPtr rmesa = R300_CONTEXT(ctx);
+	struct radeon_cs_space_check bos[16];
+	struct radeon_renderbuffer *rrb;
+	int num_bo = 0;
 	int i;
+	int flushed = 0, ret;
+again:
+	num_bo = 0;
+
+	rrb = radeon_get_colorbuffer(&rmesa->radeon);
+	/* color buffer */
+	if (rrb && rrb->bo) {
+		bos[num_bo].bo = rrb->bo;
+		bos[num_bo].read_domains = 0;
+		bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
+		bos[num_bo].new_accounted = 0;
+		num_bo++;
+	}
 
+	/* depth buffer */
+	rrb = radeon_get_depthbuffer(&rmesa->radeon);
+	/* color buffer */
+	if (rrb && rrb->bo) {
+		bos[num_bo].bo = rrb->bo;
+		bos[num_bo].read_domains = 0;
+		bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
+		bos[num_bo].new_accounted = 0;
+		num_bo++;
+	}
+	
 	for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
+		radeonTexObj *t;
+
 		if (!ctx->Texture.Unit[i]._ReallyEnabled)
 			continue;
 
@@ -280,7 +311,25 @@ void r300ValidateTextures(GLcontext * ctx)
 				      "failed to validate texture for unit %d.\n",
 				      i);
 		}
+		t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
+		bos[num_bo].bo = t->mt->bo;
+		bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
+		bos[num_bo].write_domain = 0;
+		bos[num_bo].new_accounted = 0;
+		num_bo++;
 	}
+
+	ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo);
+	if (ret == RADEON_CS_SPACE_OP_TO_BIG)
+		return GL_FALSE;
+	if (ret == RADEON_CS_SPACE_FLUSH) {
+		r300Flush(ctx);
+		if (flushed)
+			return GL_FALSE;
+		flushed = 1;
+		goto again;
+	}
+	return GL_TRUE;
 }
 
 void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,