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authorDave Airlie <[email protected]>2009-04-02 18:58:49 +1000
committerDave Airlie <[email protected]>2009-04-02 18:58:49 +1000
commit05304d41f2d9ab7a66a8b976580c156b7b93a9d3 (patch)
treee6132b7fb98ce55039ae14f539527afeb542af38 /src/mesa/drivers/dri/r300/r300_texstate.c
parent41702160090a4c1325afc07c56682f3e1c4fcaf0 (diff)
radeon/r200/r300: fix up the whole buffer space checking.
This fixes up the buffer validation scheme, so that we keep a list of buffers to validate so cmdbuf flushes during a pipeline get all the buffers revalidated on the next emit. This also fixes radeonFlush to not flush unless we have something useful to send to the GPU, like a DMA buffer or something not state
Diffstat (limited to 'src/mesa/drivers/dri/r300/r300_texstate.c')
-rw-r--r--src/mesa/drivers/dri/r300/r300_texstate.c46
1 files changed, 12 insertions, 34 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index baaca5f1e59..5a87b5da43d 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -268,40 +268,29 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object
return GL_TRUE;
}
-
/**
* Ensure all enabled and complete textures are uploaded along with any buffers being used.
*/
GLboolean r300ValidateBuffers(GLcontext * ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct radeon_cs_space_check bos[16];
struct radeon_renderbuffer *rrb;
- int num_bo = 0;
int i;
- int flushed = 0, ret;
-again:
- num_bo = 0;
+
+ radeon_validate_reset_bos(&rmesa->radeon);
rrb = radeon_get_colorbuffer(&rmesa->radeon);
/* color buffer */
if (rrb && rrb->bo) {
- bos[num_bo].bo = rrb->bo;
- bos[num_bo].read_domains = 0;
- bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
- bos[num_bo].new_accounted = 0;
- num_bo++;
+ radeon_validate_bo(&rmesa->radeon, rrb->bo,
+ 0, RADEON_GEM_DOMAIN_VRAM);
}
/* depth buffer */
rrb = radeon_get_depthbuffer(&rmesa->radeon);
- /* color buffer */
if (rrb && rrb->bo) {
- bos[num_bo].bo = rrb->bo;
- bos[num_bo].read_domains = 0;
- bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
- bos[num_bo].new_accounted = 0;
- num_bo++;
+ radeon_validate_bo(&rmesa->radeon, rrb->bo,
+ 0, RADEON_GEM_DOMAIN_VRAM);
}
for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
@@ -317,26 +306,15 @@ again:
}
t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
if (t->image_override && t->bo)
- bos[num_bo].bo = t->bo;
+ radeon_validate_bo(&rmesa->radeon, t->bo,
+ RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+
else if (t->mt->bo)
- bos[num_bo].bo = t->mt->bo;
- bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
- bos[num_bo].write_domain = 0;
- bos[num_bo].new_accounted = 0;
- num_bo++;
+ radeon_validate_bo(&rmesa->radeon, t->mt->bo,
+ RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
}
- ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo);
- if (ret == RADEON_CS_SPACE_OP_TO_BIG)
- return GL_FALSE;
- if (ret == RADEON_CS_SPACE_FLUSH) {
- radeonFlush(ctx);
- if (flushed)
- return GL_FALSE;
- flushed = 1;
- goto again;
- }
- return GL_TRUE;
+ return radeon_revalidate_bos(ctx);
}
void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,