diff options
| author | Roland Scheidegger <[email protected]> | 2012-07-27 04:03:45 +0200 |
|---|---|---|
| committer | Roland Scheidegger <[email protected]> | 2012-08-01 14:58:15 +0200 |
| commit | 5b88a2a22daae4d09596804d8edc6b8796d05150 (patch) | |
| tree | e43464f43f0c5666222a5b710e0757f1754d2885 /src/mesa/drivers/dri/r200 | |
| parent | 6574fe3c4a9e36791cde88dfd73429ba4faf3215 (diff) | |
radeon/r200: fix bogus assert/scissor wrt width/height 2048
This addresses one issue raised in bug #51658 discovered by Eugene St Leger.
The assert is bogus since there's no problem with texture width/height being
2048 (the width/height programmed is width/height minus one).
OTOH though the programmed size for scissor rect should be width/height
minus one too otherwise bad things may happen (as it is inclusive, and there's
not enough bits for more than a value of 2047).
Diffstat (limited to 'src/mesa/drivers/dri/r200')
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_blit.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c index fbded5314e5..e3124b312f4 100644 --- a/src/mesa/drivers/dri/r200/r200_blit.c +++ b/src/mesa/drivers/dri/r200/r200_blit.c @@ -108,8 +108,8 @@ static void inline emit_tx_setup(struct r200_context *r200, uint32_t txformat = R200_TXFORMAT_NON_POWER2; BATCH_LOCALS(&r200->radeon); - assert(width <= 2047); - assert(height <= 2047); + assert(width <= 2048); + assert(height <= 2048); assert(offset % 32 == 0); /* XXX others? BE/LE? */ @@ -341,8 +341,8 @@ static inline void emit_cb_setup(struct r200_context *r200, OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0); OUT_BATCH_REGVAL(R200_RE_CNTL, 0); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); - OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) | - (height << RADEON_RE_HEIGHT_SHIFT))); + OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | + ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); |