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authorDave Airlie <[email protected]>2009-04-02 14:25:07 +1000
committerDave Airlie <[email protected]>2009-04-02 14:44:29 +1000
commite00ef43d796f0ae0247b1072bf0aa8cdd8e3034d (patch)
tree252e032af38a0a37aa94b80579922e53fef262d4 /src/mesa/drivers/dri/r200
parent104d5422052d0c03b121d196f7c0a8ef0af4ecab (diff)
radeon/r200/r300: collapse context destruction down to a common path.
Context destruction was nearly the same over all the drivers, so collapse it down.
Diffstat (limited to 'src/mesa/drivers/dri/r200')
-rw-r--r--src/mesa/drivers/dri/r200/r200_cmdbuf.c96
-rw-r--r--src/mesa/drivers/dri/r200/r200_context.c58
-rw-r--r--src/mesa/drivers/dri/r200/r200_context.h6
-rw-r--r--src/mesa/drivers/dri/r200/r200_maos.h1
-rw-r--r--src/mesa/drivers/dri/r200/r200_maos_arrays.c24
-rw-r--r--src/mesa/drivers/dri/r200/r200_state.h4
-rw-r--r--src/mesa/drivers/dri/r200/r200_state_init.c16
-rw-r--r--src/mesa/drivers/dri/r200/r200_swtcl.c4
-rw-r--r--src/mesa/drivers/dri/r200/r200_swtcl.h1
-rw-r--r--src/mesa/drivers/dri/r200/r200_tcl.c16
10 files changed, 62 insertions, 164 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index 83375c88a70..3a11a448eca 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -143,18 +143,18 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
if (!rmesa->radeon.radeonScreen->kernel_mm) {
OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
- OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset,
- rmesa->tcl.elt_dma_bo,
- rmesa->tcl.elt_dma_offset,
+ OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
+ rmesa->radeon.tcl.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_count/2);
} else {
OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
- OUT_BATCH(rmesa->tcl.elt_dma_offset);
+ OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
OUT_BATCH(vertex_count/2);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.elt_dma_bo,
+ rmesa->radeon.tcl.elt_dma_bo,
RADEON_GEM_DOMAIN_GTT, 0, 0);
}
END_BATCH();
@@ -176,12 +176,12 @@ void r200FlushElts(GLcontext *ctx)
nr = elt_used / 2;
- radeon_bo_unmap(rmesa->tcl.elt_dma_bo);
+ radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
- radeon_bo_unref(rmesa->tcl.elt_dma_bo);
- rmesa->tcl.elt_dma_bo = NULL;
+ radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
+ rmesa->radeon.tcl.elt_dma_bo = NULL;
if (R200_DEBUG & DEBUG_SYNC) {
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
@@ -203,14 +203,14 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
radeonEmitState(&rmesa->radeon);
- rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
0, R200_ELT_BUF_SZ, 4,
RADEON_GEM_DOMAIN_GTT, 0);
- rmesa->tcl.elt_dma_offset = 0;
+ rmesa->radeon.tcl.elt_dma_offset = 0;
rmesa->tcl.elt_used = min_nr * 2;
- radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
- retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
+ radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
+ retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
if (R200_DEBUG & DEBUG_PRIMS)
@@ -264,79 +264,79 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
if (!rmesa->radeon.radeonScreen->kernel_mm) {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i].bo,
+ rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[nr - 1].bo,
+ rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
} else {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+0].bo,
+ rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[nr-1].bo,
+ rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 564e168290c..f80f0d8ac73 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -491,61 +491,3 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
}
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
-{
- GET_CURRENT_CONTEXT(ctx);
- r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
- r200ContextPtr current = ctx ? R200_CONTEXT(ctx) : NULL;
-
- /* check if we're deleting the currently bound context */
- if (rmesa == current) {
- radeon_firevertices(&rmesa->radeon);
- _mesa_make_current(NULL, NULL, NULL);
- }
-
- /* Free r200 context resources */
- assert(rmesa); /* should never be null */
- if ( rmesa ) {
-
- _swsetup_DestroyContext( rmesa->radeon.glCtx );
- _tnl_DestroyContext( rmesa->radeon.glCtx );
- _vbo_DestroyContext( rmesa->radeon.glCtx );
- _swrast_DestroyContext( rmesa->radeon.glCtx );
-
- r200DestroySwtcl( rmesa->radeon.glCtx );
- r200ReleaseArrays( rmesa->radeon.glCtx, ~0 );
-
- if (rmesa->radeon.dma.current) {
- radeonReleaseDmaRegion( &rmesa->radeon );
- rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
- }
-
- if (rmesa->radeon.state.scissor.pClipRects) {
- FREE(rmesa->radeon.state.scissor.pClipRects);
- rmesa->radeon.state.scissor.pClipRects = NULL;
- }
-
- radeonCleanupContext(&rmesa->radeon);
-
- FREE( rmesa );
- }
-}
-
-
-
-/* Force the context `c' to be unbound from its buffer.
- */
-GLboolean
-r200UnbindContext( __DRIcontextPrivate *driContextPriv )
-{
- r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
-
- if (R200_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx);
-
- return GL_TRUE;
-}
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index fcbe725d6fc..6267293817d 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -526,14 +526,8 @@ struct r200_state {
struct r200_tcl_info {
GLuint hw_primitive;
-/* hw can handle 12 components max */
- struct radeon_aos aos[12];
- GLuint nr_aos_components;
-
GLuint *Elts;
- struct radeon_bo *elt_dma_bo;
- int elt_dma_offset; /** Offset into this buffer object, in bytes */
int elt_used;
};
diff --git a/src/mesa/drivers/dri/r200/r200_maos.h b/src/mesa/drivers/dri/r200/r200_maos.h
index d3ed06d4021..16a70475e18 100644
--- a/src/mesa/drivers/dri/r200/r200_maos.h
+++ b/src/mesa/drivers/dri/r200/r200_maos.h
@@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_context.h"
extern void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev );
-extern void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs );
#endif
diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
index 5dbc202330b..383a0c4b0d3 100644
--- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c
+++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
@@ -142,17 +142,17 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
case 3:
/* special handling to fix up fog. Will get us into trouble with vbos...*/
assert(attrib == VERT_ATTRIB_FOG);
- if (!rmesa->tcl.aos[i].bo) {
+ if (!rmesa->radeon.tcl.aos[i].bo) {
if (ctx->VertexProgram._Enabled)
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
1,
VB->AttribPtr[attrib]->stride,
count);
else
r200_emit_vecfog( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
VB->AttribPtr[attrib]->stride,
count);
@@ -199,9 +199,9 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
default:
assert(0);
}
- if (!rmesa->tcl.aos[nr].bo) {
+ if (!rmesa->radeon.tcl.aos[nr].bo) {
rcommon_emit_vector( ctx,
- &(rmesa->tcl.aos[nr]),
+ &(rmesa->radeon.tcl.aos[nr]),
(char *)VB->AttribPtr[attrib]->data,
emitsize,
VB->AttribPtr[attrib]->stride,
@@ -220,18 +220,6 @@ after_emit:
rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1;
}
- rmesa->tcl.nr_aos_components = nr;
+ rmesa->radeon.tcl.aos_count = nr;
}
-
-void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- r200ContextPtr rmesa = R200_CONTEXT( ctx );
- int i;
- for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
- if (rmesa->tcl.aos[i].bo) {
- radeon_bo_unref(rmesa->tcl.aos[i].bo);
- rmesa->tcl.aos[i].bo = NULL;
- }
- }
-}
diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h
index 1dddbfdbfed..23cf8aea667 100644
--- a/src/mesa/drivers/dri/r200/r200_state.h
+++ b/src/mesa/drivers/dri/r200/r200_state.h
@@ -49,10 +49,6 @@ extern void r200UpdateDrawBuffer(GLcontext *ctx);
extern GLboolean r200ValidateState( GLcontext *ctx );
-extern void r200PrintDirty( r200ContextPtr rmesa,
- const char *msg );
-
-
extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
#define FALLBACK( rmesa, bit, mode ) do { \
if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 2400abe838b..75262e46bd8 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -166,22 +166,6 @@ static struct {
/* =============================================================
* State initialization
*/
-
-void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
-{
- struct radeon_state_atom *l;
-
- fprintf(stderr, msg);
- fprintf(stderr, ": ");
-
- foreach(l, &rmesa->radeon.hw.atomlist) {
- if (l->dirty || rmesa->radeon.hw.all_dirty)
- fprintf(stderr, "%s, ", l->name);
- }
-
- fprintf(stderr, "\n");
-}
-
static int cmdpkt( r200ContextPtr rmesa, int id )
{
drm_radeon_cmd_header_t h;
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index b006409987a..712da980775 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -908,7 +908,3 @@ void r200InitSwtcl( GLcontext *ctx )
rmesa->radeon.swtcl.hw_primitive = 0;
}
-
-void r200DestroySwtcl( GLcontext *ctx )
-{
-}
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h
index a4051a4b768..b0905879d7a 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.h
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.h
@@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_context.h"
extern void r200InitSwtcl( GLcontext *ctx );
-extern void r200DestroySwtcl( GLcontext *ctx );
extern void r200ChooseRenderState( GLcontext *ctx );
extern void r200ChooseVertexState( GLcontext *ctx );
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index 8e0fb14e70e..580370933ee 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -145,7 +145,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
if (rmesa->radeon.dma.flush == r200FlushElts &&
rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
- GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr +
+ GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
rmesa->tcl.elt_used);
rmesa->tcl.elt_used += nr*2;
@@ -156,10 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
if (rmesa->radeon.dma.flush)
rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
- rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
+ rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
r200EmitAOS( rmesa,
- rmesa->tcl.nr_aos_components, 0 );
+ rmesa->radeon.tcl.aos_count, 0 );
return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
}
@@ -186,13 +186,13 @@ static void r200EmitPrim( GLcontext *ctx,
r200ContextPtr rmesa = R200_CONTEXT( ctx );
r200TclPrimitive( ctx, prim, hwprim );
- // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components);
+ // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
rcommonEnsureCmdBufSpace( &rmesa->radeon,
- AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+ AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
r200EmitAOS( rmesa,
- rmesa->tcl.nr_aos_components,
+ rmesa->radeon.tcl.aos_count,
start );
/* Why couldn't this packet have taken an offset param?
@@ -481,7 +481,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx,
/* Do the actual work:
*/
- r200ReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
+ radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
r200EmitArrays( ctx, vimap_rev );
rmesa->tcl.Elts = VB->Elts;
@@ -545,7 +545,7 @@ static void transition_to_swtnl( GLcontext *ctx )
tnl->Driver.NotifyMaterialChange =
_mesa_validate_all_lighting_tables;
- r200ReleaseArrays( ctx, ~0 );
+ radeonReleaseArrays( ctx, ~0 );
/* Still using the D3D based hardware-rasterizer from the radeon;
* need to put the card into D3D mode to make it work: