intel: Replace mt->pitch with mt->region->pitch.

The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.

6 files changed, 21 insertions, 88 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index ba3bb8fdba4..8278d12bb90 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -568,7 +568,7 @@ intel_render_texture(GLcontext * ctx,
 				  att->Zoffset,
 				  &dst_x, &dst_y);
 
-   intel_image->mt->region->draw_offset = (dst_y * intel_image->mt->pitch +
+   intel_image->mt->region->draw_offset = (dst_y * intel_image->mt->region->pitch +
 					   dst_x) * intel_image->mt->cpp;
    intel_image->mt->region->draw_x = dst_x;
    intel_image->mt->region->draw_y = dst_y;
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index e02b188e354..e671355c381 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -83,7 +83,6 @@ intel_miptree_create_internal(struct intel_context *intel,
    mt->cpp = compress_byte ? compress_byte : cpp;
    mt->compressed = compress_byte ? 1 : 0;
    mt->refcount = 1; 
-   mt->pitch = 0;
 
 #ifdef I915
    if (intel->is_945)
@@ -136,7 +135,7 @@ intel_miptree_create(struct intel_context *intel,
    /*
     * pitch == 0 || height == 0  indicates the null texture
     */
-   if (!mt || !mt->pitch || !mt->total_height) {
+   if (!mt || !mt->total_height) {
       free(mt);
       return NULL;
    }
@@ -144,10 +143,9 @@ intel_miptree_create(struct intel_context *intel,
    mt->region = intel_region_alloc(intel,
 				   tiling,
 				   mt->cpp,
-				   mt->pitch,
+				   mt->total_width,
 				   mt->total_height,
 				   expect_accelerated_upload);
-   mt->pitch = mt->region->pitch;
 
    if (!mt->region) {
        free(mt);
@@ -178,71 +176,11 @@ intel_miptree_create_for_region(struct intel_context *intel,
    if (!mt)
       return mt;
 
-   /* The mipmap tree pitch is aligned to 64 bytes to make sure render
-    * to texture works, but we don't need that for texturing from a
-    * pixmap.  Just override it here. */
-   mt->pitch = region->pitch;
-
    intel_region_reference(&mt->region, region);
 
    return mt;
 }
 
-
-/**
- * intel_miptree_pitch_align:
- *
- * @intel: intel context pointer
- *
- * @mt: the miptree to compute pitch alignment for
- *
- * @pitch: the natural pitch value
- *
- * Given @pitch, compute a larger value which accounts for
- * any necessary alignment required by the device
- */
-int intel_miptree_pitch_align (struct intel_context *intel,
-			       struct intel_mipmap_tree *mt,
-			       uint32_t tiling,
-			       int pitch)
-{
-#ifdef I915
-   GLcontext *ctx = &intel->ctx;
-#endif
-
-   if (!mt->compressed) {
-      int pitch_align;
-
-      /* XXX: Align pitch to multiple of 64 bytes for now to allow
-       * render-to-texture to work in all cases. This should probably be
-       * replaced at some point by some scheme to only do this when really
-       * necessary.
-       */
-      pitch_align = 64;
-
-      if (tiling == I915_TILING_X)
-	 pitch_align = 512;
-      else if (tiling == I915_TILING_Y)
-	 pitch_align = 128;
-
-      pitch = ALIGN(pitch * mt->cpp, pitch_align);
-
-#ifdef I915
-      /* Do a little adjustment to linear allocations so that we avoid
-       * hitting the same channel of memory for 2 different pages when
-       * reading a 2x2 subspan or doing bilinear filtering.
-       */
-      if (tiling == I915_TILING_NONE && !(pitch & 511) &&
-	 (pitch + pitch_align) < (1 << ctx->Const.MaxTextureLevels))
-	 pitch += pitch_align;
-#endif
-
-      pitch /= mt->cpp;
-   }
-   return pitch;
-}
-
-
 void
 intel_miptree_reference(struct intel_mipmap_tree **dst,
                         struct intel_mipmap_tree *src)
@@ -414,7 +352,7 @@ intel_miptree_image_map(struct intel_context * intel,
    DBG("%s \n", __FUNCTION__);
 
    if (row_stride)
-      *row_stride = mt->pitch * mt->cpp;
+      *row_stride = mt->region->pitch * mt->cpp;
 
    if (mt->target == GL_TEXTURE_3D) {
       int i;
@@ -423,7 +361,7 @@ intel_miptree_image_map(struct intel_context * intel,
 
 	 intel_miptree_get_image_offset(mt, level, face, i,
 					&x, &y);
-	 image_offsets[i] = x + y * mt->pitch;
+	 image_offsets[i] = x + y * mt->region->pitch;
       }
 
       return intel_region_map(intel, mt->region);
@@ -434,7 +372,7 @@ intel_miptree_image_map(struct intel_context * intel,
       image_offsets[0] = 0;
 
       return intel_region_map(intel, mt->region) +
-	 (x + y * mt->pitch) * mt->cpp;
+	 (x + y * mt->region->pitch) * mt->cpp;
    }
 }
 
@@ -524,13 +462,13 @@ intel_miptree_image_copy(struct intel_context *intel,
 	 src_ptr = intel_region_map(intel, src->region);
 	 dst_ptr = intel_region_map(intel, dst->region);
 
-	 _mesa_copy_rect(dst_ptr + dst->cpp * (dst_x + dst_y * dst->pitch),
+	 _mesa_copy_rect(dst_ptr,
 			 dst->cpp,
-			 dst->pitch,
-			 0, 0, width, height,
-			 src_ptr + src->cpp * (src_x + src_y * src->pitch),
-			 src->pitch,
-			 0, 0);
+			 dst->region->pitch,
+			 dst_x, dst_y, width, height,
+			 src_ptr,
+			 src->region->pitch,
+			 src_x, src_y);
 	 intel_region_unmap(intel, src->region);
 	 intel_region_unmap(intel, dst->region);
       }
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 7f3468f1153..21db2f4d3b3 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -102,8 +102,7 @@ struct intel_mipmap_tree
 
    /* Derived from the above:
     */
-   GLuint pitch;
-   GLuint depth_pitch;          /* per-image on i945? */
+   GLuint total_width;
    GLuint total_height;
 
    /* Includes image offset tables:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 13b8bcfa86c..618f690a5f8 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -155,7 +155,7 @@ do_copy_texsubimage(struct intel_context *intel,
 			     src->buffer,
 			     0,
 			     src->tiling,
-			     intelImage->mt->pitch,
+			     intelImage->mt->region->pitch,
 			     dst_bo,
 			     0,
 			     intelImage->mt->region->tiling,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index bac36eeb569..9db96acdc08 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -236,7 +236,7 @@ try_pbo_upload(struct intel_context *intel,
 				  intelImage->face, 0,
 				  &dst_x, &dst_y);
 
-   dst_stride = intelImage->mt->pitch;
+   dst_stride = intelImage->mt->region->pitch;
 
    if (drm_intel_bo_references(intel->batch->buf, dst_buffer))
       intelFlush(&intel->ctx);
@@ -290,7 +290,7 @@ try_pbo_zcopy(struct intel_context *intel,
 				  intelImage->face, 0,
 				  &dst_x, &dst_y);
 
-   dst_stride = intelImage->mt->pitch;
+   dst_stride = intelImage->mt->region->pitch;
 
    if (src_stride != dst_stride || dst_x != 0 || dst_y != 0 ||
        src_offset != 0) {
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 7d69ea4484a..d132e19e831 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -74,14 +74,14 @@ void i945_miptree_layout_2d( struct intel_context *intel,
    GLuint width = mt->width0;
    GLuint height = mt->height0;
 
-   mt->pitch = mt->width0;
+   mt->total_width = mt->width0;
    intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
 
    if (mt->compressed) {
-       mt->pitch = ALIGN(mt->width0, align_w);
+       mt->total_width = ALIGN(mt->width0, align_w);
    }
 
-   /* May need to adjust pitch to accomodate the placement of
+   /* May need to adjust width to accomodate the placement of
     * the 2nd mipmap.  This occurs when the alignment
     * constraints of mipmap placement push the right edge of the
     * 2nd mipmap out past the width of its parent.
@@ -97,15 +97,11 @@ void i945_miptree_layout_2d( struct intel_context *intel,
                + minify(minify(mt->width0));
        }
 
-       if (mip1_width > mt->pitch) {
-           mt->pitch = mip1_width;
+       if (mip1_width > mt->total_width) {
+           mt->total_width = mip1_width;
        }
    }
 
-   /* Pitch must be a whole number of dwords, even though we
-    * express it in texels.
-    */
-   mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->pitch);
    mt->total_height = 0;
 
    for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {