diff options
| author | Kenneth Graunke <[email protected]> | 2012-07-26 11:41:26 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-08-08 09:23:57 -0700 |
| commit | 61d0b9f52c6be4a4a64c30ea3a2a93ef8260c67b (patch) | |
| tree | 2a3df54a8fdefeae4a523636f58d928bcab5b344 /src/mesa/drivers/dri/intel | |
| parent | ecac178aa2591afc36e5d34d11a773ff07cb71b1 (diff) | |
intel: Make the length for PIPE_CONTROL explicit.
PIPE_CONTROL has variable length, depending upon generation and whether
we want to do 32-bit or 64-bit data writes. Make it explicit, rather
than hiding a length of 4 in the #define for _3DSTATE_PIPE_CONTROL.
Generated by s/3DSTATE_PIPE_CONTROL/3DSTATE_PIPE_CONTROL | (4 - 2)/g.
This is equivalent since the #define used to have | 2 in it. A grep
through the sources shows that all instances have been converted, so
it's safe to remove the | 2 from the #define.
Signed-off-by: Daniel Vetter <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/intel')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_batchbuffer.c | 16 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_reg.h | 2 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index a1b5ccc4204..ac133ee8e03 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -380,21 +380,21 @@ intel_emit_depth_stall_flushes(struct intel_context *intel) assert(intel->gen >= 6 && intel->gen <= 7); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ ADVANCE_BATCH() BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ @@ -415,7 +415,7 @@ gen7_emit_vs_workaround_flush(struct intel_context *intel) assert(intel->gen == 7); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(intel->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); @@ -467,7 +467,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) return; BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); OUT_BATCH(0); /* address */ @@ -475,7 +475,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) ADVANCE_BATCH(); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(intel->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); @@ -514,7 +514,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel) } BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | @@ -528,7 +528,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel) } } else if (intel->gen >= 4) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_NO_WRITE); OUT_BATCH(0); /* write address */ diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h index e2a6ee20311..2c75a8e35d5 100644 --- a/src/mesa/drivers/dri/intel/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -58,7 +58,7 @@ * PIPE_CONTROL operation, a combination MI_FLUSH and register write with * additional flushing control. */ -#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2) +#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) #define PIPE_CONTROL_CS_STALL (1 << 20) #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) #define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) |