Revert "Revert "Merge branch 'drm-gem'""

This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.

1 files changed, 541 insertions, 135 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 742b1b87350..edede3a74b4 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -39,6 +39,224 @@
 
 #include "swrast/swrast.h"
 
+static void
+intel_set_span_functions(struct intel_context *intel,
+			 struct gl_renderbuffer *rb);
+
+#define SPAN_CACHE_SIZE		4096
+
+static void
+get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
+{
+   if (irb->span_cache == NULL) {
+      irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
+      irb->span_cache_offset = -1;
+   }
+
+   if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
+      irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
+      dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
+			 SPAN_CACHE_SIZE, irb->span_cache);
+   }
+}
+
+static void
+clear_span_cache(struct intel_renderbuffer *irb)
+{
+   irb->span_cache_offset = -1;
+}
+
+static uint32_t
+pread_32(struct intel_renderbuffer *irb, uint32_t offset)
+{
+   get_span_cache(irb, offset);
+
+   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
+}
+
+static uint32_t
+pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
+{
+   get_span_cache(irb, offset);
+
+   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
+      0xff000000;
+}
+
+static uint16_t
+pread_16(struct intel_renderbuffer *irb, uint32_t offset)
+{
+   get_span_cache(irb, offset);
+
+   return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
+}
+
+static uint8_t
+pread_8(struct intel_renderbuffer *irb, uint32_t offset)
+{
+   get_span_cache(irb, offset);
+
+   return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
+}
+
+static void
+pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
+{
+   clear_span_cache(irb);
+
+   dri_bo_subdata(irb->region->buffer, offset, 4, &val);
+}
+
+static void
+pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
+{
+   clear_span_cache(irb);
+
+   dri_bo_subdata(irb->region->buffer, offset, 3, &val);
+}
+
+static void
+pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
+{
+   clear_span_cache(irb);
+
+   dri_bo_subdata(irb->region->buffer, offset, 2, &val);
+}
+
+static void
+pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
+{
+   clear_span_cache(irb);
+
+   dri_bo_subdata(irb->region->buffer, offset, 1, &val);
+}
+
+static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
+				struct intel_context *intel,
+				int x, int y)
+{
+	x += intel->drawX;
+	y += intel->drawY;
+
+	return (y * irb->region->pitch + x) * irb->region->cpp;
+}
+
+/*
+ * Deal with tiled surfaces
+ */
+
+static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
+			       struct intel_context *intel,
+			       int x, int y)
+{
+	int	tile_stride;
+	int	xbyte;
+	int	x_tile_off, y_tile_off;
+	int	x_tile_number, y_tile_number;
+	int	tile_off, tile_base;
+	
+	tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+	
+	x += intel->drawX;
+	y += intel->drawY;
+
+	xbyte = x * irb->region->cpp;
+
+	x_tile_off = xbyte & 0x1ff;
+	y_tile_off = y & 7;
+
+	x_tile_number = xbyte >> 9;
+	y_tile_number = y >> 3;
+
+	tile_off = (y_tile_off << 9) + x_tile_off;
+
+	switch (irb->region->bit_6_swizzle) {
+	case I915_BIT_6_SWIZZLE_NONE:
+	   break;
+	case I915_BIT_6_SWIZZLE_9:
+	   tile_off ^= ((tile_off >> 3) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_10:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_11:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_10_11:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
+	      ((tile_off >> 5) & 64);
+	   break;
+	default:
+	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
+		   irb->region->bit_6_swizzle);
+	   exit(1);
+	}
+
+	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+
+#if 0
+	printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
+	       x, y, tile_off, tile_base,
+	       tile_off + tile_base,
+	       irb->pfPitch, tile_stride);
+#endif
+
+	return tile_base + tile_off;
+}
+
+static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
+			       struct intel_context *intel,
+			       int x, int y)
+{
+	int	tile_stride;
+	int	xbyte;
+	int	x_tile_off, y_tile_off;
+	int	x_tile_number, y_tile_number;
+	int	tile_off, tile_base;
+	
+	tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
+	
+	x += intel->drawX;
+	y += intel->drawY;
+
+	xbyte = x * irb->region->cpp;
+
+	x_tile_off = xbyte & 0x7f;
+	y_tile_off = y & 0x1f;
+
+	x_tile_number = xbyte >> 7;
+	y_tile_number = y >> 5;
+
+	tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
+	   (x_tile_off & 0xf);
+
+	switch (irb->region->bit_6_swizzle) {
+	case I915_BIT_6_SWIZZLE_NONE:
+	   break;
+	case I915_BIT_6_SWIZZLE_9:
+	   tile_off ^= ((tile_off >> 3) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_10:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_11:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
+	   break;
+	case I915_BIT_6_SWIZZLE_9_10_11:
+	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
+	      ((tile_off >> 5) & 64);
+	   break;
+	default:
+	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
+		   irb->region->bit_6_swizzle);
+	   exit(1);
+	}
+
+	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+
+	return tile_base + tile_off;
+}
+
 /*
   break intelWriteRGBASpan_ARGB8888
 */
@@ -51,10 +269,7 @@
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);		\
    const GLint yScale = irb->RenderToTexture ? 1 : -1;			\
    const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;	\
-   GLubyte *buf = (GLubyte *) irb->pfMap				\
-      + (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\
    GLuint p;								\
-   assert(irb->pfMap);\
    (void) p;
 
 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
@@ -69,12 +284,14 @@
 	 int miny = intel->pClipRects[_nc].y1 - intel->drawY;		\
 	 int maxx = intel->pClipRects[_nc].x2 - intel->drawX;		\
 	 int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
-
-
-
+	
+#if 0
+      }}
+#endif
 
 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 
+/* XXX with GEM, these need to tell the kernel */
 #define HW_LOCK()
 
 #define HW_UNLOCK()
@@ -86,7 +303,8 @@
 
 #define TAG(x)    intel##x##_RGB565
 #define TAG2(x,y) intel##x##_RGB565##y
-#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 2)
+#define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V)
 #include "spantmp2.h"
 
 /* 32 bit, ARGB8888 color spanline and pixel functions
@@ -96,17 +314,89 @@
 
 #define TAG(x)    intel##x##_ARGB8888
 #define TAG2(x,y) intel##x##_ARGB8888##y
-#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4)
+#define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+/* 32 bit, xRGB8888 color spanline and pixel functions
+ */
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x)    intel##x##_xRGB8888
+#define TAG2(x,y) intel##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+/* 16 bit RGB565 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+
+#define TAG(x)    intel_XTile_##x##_RGB565
+#define TAG2(x,y) intel_XTile_##x##_RGB565##y
+#define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+
+#define TAG(x)    intel_YTile_##x##_RGB565
+#define TAG2(x,y) intel_YTile_##x##_RGB565##y
+#define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+/* 32 bit ARGB888 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x)    intel_XTile_##x##_ARGB8888
+#define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
+#define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x)    intel_YTile_##x##_ARGB8888
+#define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
+#define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+/* 32 bit xRGB888 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x)    intel_XTile_##x##_xRGB8888
+#define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x)    intel_YTile_##x##_xRGB8888
+#define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
 #include "spantmp2.h"
 
 #define LOCAL_DEPTH_VARS						\
    struct intel_context *intel = intel_context(ctx);			\
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);		\
-   const GLuint pitch = irb->pfPitch/***XXX region->pitch*/; /* in pixels */ \
    const GLint yScale = irb->RenderToTexture ? 1 : -1;			\
-   const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;	\
-   char *buf = (char *) irb->pfMap/*XXX use region->map*/ +             \
-      (intel->drawY * pitch + intel->drawX) * irb->region->cpp;
+   const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;
 
 
 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
@@ -115,15 +405,34 @@
  ** 16-bit depthbuffer functions.
  **/
 #define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+   pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+   d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y))
+#define TAG(x) intel##x##_z16
+#include "depthtmp.h"
 
-#define WRITE_DEPTH( _x, _y, d ) \
-   ((GLushort *)buf)[(_x) + (_y) * pitch] = d;
-
-#define READ_DEPTH( d, _x, _y )	\
-   d = ((GLushort *)buf)[(_x) + (_y) * pitch];
 
+/**
+ ** 16-bit x tile depthbuffer functions.
+ **/
+#define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+   pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+   d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y))
+#define TAG(x) intel_XTile_##x##_z16
+#include "depthtmp.h"
 
-#define TAG(x) intel##x##_z16
+/**
+ ** 16-bit y tile depthbuffer functions.
+ **/
+#define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+   pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+   d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y))
+#define TAG(x) intel_YTile_##x##_z16
 #include "depthtmp.h"
 
 
@@ -136,14 +445,13 @@
 #define VALUE_TYPE GLuint
 
 /* Change ZZZS -> SZZZ */
-#define WRITE_DEPTH( _x, _y, d ) {				\
-   GLuint tmp = ((d) >> 8) | ((d) << 24);			\
-   ((GLuint *)buf)[(_x) + (_y) * pitch] = tmp;			\
-}
+#define WRITE_DEPTH(_x, _y, d)					\
+   pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y),		\
+	     ((d) >> 8) | ((d) << 24))
 
 /* Change SZZZ -> ZZZS */
 #define READ_DEPTH( d, _x, _y ) {				\
-   GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch];		\
+   GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y));	\
    d = (tmp << 8) | (tmp >> 24);				\
 }
 
@@ -152,22 +460,114 @@
 
 
 /**
- ** 8-bit stencil function (XXX FBO: This is obsolete)
+ ** 24/8-bit x-tile interleaved depth/stencil functions
+ ** Note: we're actually reading back combined depth+stencil values.
+ ** The wrappers in main/depthstencil.c are used to extract the depth
+ ** and stencil values.
  **/
-#define WRITE_STENCIL( _x, _y, d ) {				\
-   GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch];		\
-   tmp &= 0xffffff;						\
-   tmp |= ((d) << 24);						\
-   ((GLuint *) buf)[(_x) + (_y) * pitch] = tmp;			\
+#define VALUE_TYPE GLuint
+
+/* Change ZZZS -> SZZZ */
+#define WRITE_DEPTH(_x, _y, d)					\
+   pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y),		\
+	     ((d) >> 8) | ((d) << 24))				\
+
+/* Change SZZZ -> ZZZS */
+#define READ_DEPTH( d, _x, _y ) {				\
+   GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y));	\
+   d = (tmp << 8) | (tmp >> 24);				\
 }
 
-#define READ_STENCIL( d, _x, _y )				\
-   d = ((GLuint *)buf)[(_x) + (_y) * pitch] >> 24;
+#define TAG(x) intel_XTile_##x##_z24_s8
+#include "depthtmp.h"
+
+/**
+ ** 24/8-bit y-tile interleaved depth/stencil functions
+ ** Note: we're actually reading back combined depth+stencil values.
+ ** The wrappers in main/depthstencil.c are used to extract the depth
+ ** and stencil values.
+ **/
+#define VALUE_TYPE GLuint
+
+/* Change ZZZS -> SZZZ */
+#define WRITE_DEPTH(_x, _y, d)					\
+   pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y),		\
+	     ((d) >> 8) | ((d) << 24))
+
+/* Change SZZZ -> ZZZS */
+#define READ_DEPTH( d, _x, _y ) {				\
+   GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y));	\
+   d = (tmp << 8) | (tmp >> 24);				\
+}
+
+#define TAG(x) intel_YTile_##x##_z24_s8
+#include "depthtmp.h"
+
+
+/**
+ ** 8-bit stencil function (XXX FBO: This is obsolete)
+ **/
+#define WRITE_STENCIL(_x, _y, d)				\
+   pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d)
+
+#define READ_STENCIL(d, _x, _y)					\
+   d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3);
 
 #define TAG(x) intel##x##_z24_s8
 #include "stenciltmp.h"
 
+/**
+ ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
+ **/
+#define WRITE_STENCIL(_x, _y, d)				\
+   pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d)
 
+#define READ_STENCIL(d, _x, _y)					\
+   d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3);
+
+#define TAG(x) intel_XTile_##x##_z24_s8
+#include "stenciltmp.h"
+
+/**
+ ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
+ **/
+#define WRITE_STENCIL(_x, _y, d)				\
+   pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d)
+
+#define READ_STENCIL(d, _x, _y)					\
+   d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3)
+
+#define TAG(x) intel_YTile_##x##_z24_s8
+#include "stenciltmp.h"
+
+void
+intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
+{
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+   if (irb == NULL || irb->region == NULL)
+      return;
+
+   irb->pfPitch = irb->region->pitch;
+
+   intel_set_span_functions(intel, rb);
+}
+
+void
+intel_renderbuffer_unmap(struct intel_context *intel,
+			 struct gl_renderbuffer *rb)
+{
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+   if (irb == NULL || irb->region == NULL)
+      return;
+
+   clear_span_cache(irb);
+   irb->pfPitch = 0;
+
+   rb->GetRow = NULL;
+   rb->PutRow = NULL;
+}
 
 /**
  * Map or unmap all the renderbuffers which we may need during
@@ -186,23 +586,13 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
 {
    GLcontext *ctx = &intel->ctx;
    GLuint i, j;
-   struct intel_renderbuffer *irb;
 
    /* color draw buffers */
    for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
-      struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
-      irb = intel_renderbuffer(rb);
-      if (irb) {
-         /* this is a user-created intel_renderbuffer */
-         if (irb->region) {
-            if (map)
-               intel_region_map(intel, irb->region);
-            else
-               intel_region_unmap(intel, irb->region);
-            irb->pfMap = irb->region->map;
-            irb->pfPitch = irb->region->pitch;
-         }
-      }
+      if (map)
+	 intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+      else
+	 intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
    }
 
    /* check for render to textures */
@@ -225,77 +615,28 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
    }
 
    /* color read buffers */
-   irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
-   if (irb && irb->region) {
-      if (map)
-         intel_region_map(intel, irb->region);
-      else
-         intel_region_unmap(intel, irb->region);
-      irb->pfMap = irb->region->map;
-      irb->pfPitch = irb->region->pitch;
-   }
-
-   /* Account for front/back color page flipping.
-    * The span routines use the pfMap and pfPitch fields which will
-    * swap the front/back region map/pitch if we're page flipped.
-    * Do this after mapping, above, so the map field is valid.
-    */
-#if 0
-   if (map && ctx->DrawBuffer->Name == 0) {
-      struct intel_renderbuffer *irbFront
-         = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_FRONT_LEFT);
-      struct intel_renderbuffer *irbBack
-         = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_BACK_LEFT);
-      if (irbBack) {
-         /* double buffered */
-         if (intel->sarea->pf_current_page == 0) {
-            irbFront->pfMap = irbFront->region->map;
-            irbFront->pfPitch = irbFront->region->pitch;
-            irbBack->pfMap = irbBack->region->map;
-            irbBack->pfPitch = irbBack->region->pitch;
-         }
-         else {
-            irbFront->pfMap = irbBack->region->map;
-            irbFront->pfPitch = irbBack->region->pitch;
-            irbBack->pfMap = irbFront->region->map;
-            irbBack->pfPitch = irbFront->region->pitch;
-         }
-      }
-   }
-#endif
+   if (map)
+      intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
+   else
+      intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
 
    /* depth buffer (Note wrapper!) */
    if (ctx->DrawBuffer->_DepthBuffer) {
-      irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
-      if (irb && irb->region) {
-         if (map) {
-            intel_region_map(intel, irb->region);
-            irb->pfMap = irb->region->map;
-            irb->pfPitch = irb->region->pitch;
-         }
-         else {
-            intel_region_unmap(intel, irb->region);
-            irb->pfMap = irb->region->map;
-            irb->pfPitch = irb->region->pitch;
-         }
-      }
+      if (map)
+	 intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
+      else
+	 intel_renderbuffer_unmap(intel,
+				  ctx->DrawBuffer->_DepthBuffer->Wrapped);
    }
 
    /* stencil buffer (Note wrapper!) */
    if (ctx->DrawBuffer->_StencilBuffer) {
-      irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
-      if (irb && irb->region) {
-         if (map) {
-            intel_region_map(intel, irb->region);
-            irb->pfMap = irb->region->map;
-            irb->pfPitch = irb->region->pitch;
-         }
-         else {
-            intel_region_unmap(intel, irb->region);
-            irb->pfMap = irb->region->map;
-            irb->pfPitch = irb->region->pitch;
-         }
-      }
+      if (map)
+	 intel_renderbuffer_map(intel,
+				ctx->DrawBuffer->_StencilBuffer->Wrapped);
+      else
+	 intel_renderbuffer_unmap(intel,
+				  ctx->DrawBuffer->_StencilBuffer->Wrapped);
    }
 }
 
@@ -313,18 +654,9 @@ intelSpanRenderStart(GLcontext * ctx)
    struct intel_context *intel = intel_context(ctx);
    GLuint i;
 
-   intelFinish(&intel->ctx);
+   intelFlush(&intel->ctx);
    LOCK_HARDWARE(intel);
 
-#if 0
-   /* Just map the framebuffer and all textures.  Bufmgr code will
-    * take care of waiting on the necessary fences:
-    */
-   intel_region_map(intel, intel->front_region);
-   intel_region_map(intel, intel->back_region);
-   intel_region_map(intel, intel->depth_region);
-#endif
-
    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
       if (ctx->Texture.Unit[i]._ReallyEnabled) {
          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -347,14 +679,6 @@ intelSpanRenderFinish(GLcontext * ctx)
 
    _swrast_flush(ctx);
 
-   /* Now unmap the framebuffer:
-    */
-#if 0
-   intel_region_unmap(intel, intel->front_region);
-   intel_region_unmap(intel, intel->back_region);
-   intel_region_unmap(intel, intel->depth_region);
-#endif
-
    for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
       if (ctx->Texture.Unit[i]._ReallyEnabled) {
          struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -381,26 +705,108 @@ intelInitSpanFuncs(GLcontext * ctx)
  * Plug in appropriate span read/write functions for the given renderbuffer.
  * These are used for the software fallbacks.
  */
-void
-intel_set_span_functions(struct gl_renderbuffer *rb)
+static void
+intel_set_span_functions(struct intel_context *intel,
+			 struct gl_renderbuffer *rb)
 {
+   struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
+   uint32_t tiling;
+
+   /* If in GEM mode, we need to do the tile address swizzling ourselves,
+    * instead of the fence registers handling it.
+    */
+   if (intel->ttm)
+      tiling = irb->region->tiling;
+   else
+      tiling = I915_TILING_NONE;
+
    if (rb->_ActualFormat == GL_RGB5) {
       /* 565 RGB */
-      intelInitPointers_RGB565(rb);
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitPointers_RGB565(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitPointers_RGB565(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitPointers_RGB565(rb);
+	 break;
+      }
+   }
+   else if (rb->_ActualFormat == GL_RGB8) {
+      /* 8888 RGBx */
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitPointers_xRGB8888(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitPointers_xRGB8888(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitPointers_xRGB8888(rb);
+	 break;
+      }
    }
    else if (rb->_ActualFormat == GL_RGBA8) {
       /* 8888 RGBA */
-      intelInitPointers_ARGB8888(rb);
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitPointers_ARGB8888(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitPointers_ARGB8888(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitPointers_ARGB8888(rb);
+	 break;
+      }
    }
    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
-      intelInitDepthPointers_z16(rb);
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitDepthPointers_z16(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitDepthPointers_z16(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitDepthPointers_z16(rb);
+	 break;
+      }
    }
    else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 ||        /* XXX FBO remove */
             rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
-      intelInitDepthPointers_z24_s8(rb);
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitDepthPointers_z24_s8(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitDepthPointers_z24_s8(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitDepthPointers_z24_s8(rb);
+	 break;
+      }
    }
-   else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {       /* XXX FBO remove */
-      intelInitStencilPointers_z24_s8(rb);
+   else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+	 intelInitStencilPointers_z24_s8(rb);
+	 break;
+      case I915_TILING_X:
+	 intel_XTile_InitStencilPointers_z24_s8(rb);
+	 break;
+      case I915_TILING_Y:
+	 intel_YTile_InitStencilPointers_z24_s8(rb);
+	 break;
+      }
    }
    else {
       _mesa_problem(NULL,