diff options
| author | Eric Anholt <[email protected]> | 2011-06-17 18:24:56 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2011-06-20 08:37:43 -0700 |
| commit | 0ab7d6f437f2f7a1b2d84f30497f3c2013b52791 (patch) | |
| tree | 7afaf4d07ede5d262bf13c5b3fbd32e7b49bd97d /src/mesa/drivers/dri/intel/intel_batchbuffer.c | |
| parent | dfada714f8db3deea2fea3583c3c166a78db1117 (diff) | |
i965/gen6: Limit the workaround flush to once per primitive.
We're about to call this function in a bunch of state emits, so let's
not spam the hardware with flushes too hard.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_batchbuffer.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_batchbuffer.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 9e8f8b5eefd..77563aefdc5 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -296,6 +296,9 @@ emit: static void intel_emit_post_sync_nonzero_flush(struct intel_context *intel) { + if (!intel->batch.need_workaround_flush) + return; + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); @@ -303,6 +306,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0); OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); + + intel->batch.need_workaround_flush = false; } /* Emit a pipelined flush to either flush render and texture cache for |