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authorIan Romanick <[email protected]>2015-06-22 11:09:27 -0700
committerIan Romanick <[email protected]>2015-06-24 16:33:32 -0700
commit9f261dc18dba0aa4dc43fc560d343ba9ffd486e9 (patch)
treeed077edd2def4603bdb93e88fe468231f5f59f41 /src/mesa/drivers/dri/i965
parentb2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea (diff)
radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED value
Commit b765119c changed the default value of all the counter bits to 64. However, older hardware only has 32 counter bits. This has only been build-tested. We don't have any tests that verify the advertised value against implementation behavior, so I don't know what additional testing could be done. NOTE: It appears that many Gallium drivers (at least r300 and i915g) have the same problem, but I don't see a way for the state-tracker to determine the counter size. Marek says, "For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed." Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: Alex Deucher <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
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