i965: add SHADER_OPCODE_TG4

Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().

V3: Updated for changes in master.

Signed-off-by: Chris Forbes <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

6 files changed, 17 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index b14c346abe6..ae2839ad7cf 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -767,6 +767,7 @@ enum opcode {
    FS_OPCODE_TXB,
    SHADER_OPCODE_TXF_MS,
    SHADER_OPCODE_LOD,
+   SHADER_OPCODE_TG4,
 
    SHADER_OPCODE_SHADER_TIME_ADD,
 
@@ -1042,8 +1043,10 @@ enum brw_message_target {
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
+#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
 #define GEN5_SAMPLER_MESSAGE_LOD                 9
 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
+#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0b441d451f1..89eb33e480d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -725,6 +725,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case SHADER_OPCODE_TXD:
    case SHADER_OPCODE_TXF:
    case SHADER_OPCODE_TXF_MS:
+   case SHADER_OPCODE_TG4:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_LOD:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 9eb5e177928..5672eaee915 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -431,6 +431,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       case SHADER_OPCODE_LOD:
          msg_type = GEN5_SAMPLER_MESSAGE_LOD;
          break;
+      case SHADER_OPCODE_TG4:
+         assert(brw->gen >= 6);
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
+         break;
       default:
 	 assert(!"not reached");
 	 break;
@@ -1403,6 +1407,7 @@ fs_generator::generate_code(exec_list *instructions)
       case SHADER_OPCODE_TXL:
       case SHADER_OPCODE_TXS:
       case SHADER_OPCODE_LOD:
+      case SHADER_OPCODE_TG4:
 	 generate_tex(inst, dst, src[0]);
 	 break;
       case FS_OPCODE_DDX:
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index a558d3604a3..61c4bf5a5ff 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -532,7 +532,8 @@ backend_instruction::is_tex()
            opcode == SHADER_OPCODE_TXF_MS ||
            opcode == SHADER_OPCODE_TXL ||
            opcode == SHADER_OPCODE_TXS ||
-           opcode == SHADER_OPCODE_LOD);
+           opcode == SHADER_OPCODE_LOD ||
+           opcode == SHADER_OPCODE_TG4);
 }
 
 bool
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 2c1f54158b7..75c3d344b5e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -270,6 +270,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case SHADER_OPCODE_TXF:
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXS:
+   case SHADER_OPCODE_TG4:
       return inst->header_present ? 1 : 0;
    default:
       assert(!"not reached");
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 6916134c1ac..6bdffb39392 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -308,6 +308,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TXS:
 	 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 	 break;
+      case SHADER_OPCODE_TG4:
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
+         break;
       default:
 	 assert(!"should not get here: invalid VS texture opcode");
 	 break;
@@ -361,7 +364,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       brw_MOV(p,
 	      retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
 		     BRW_REGISTER_TYPE_UD),
-	      brw_imm_uw(inst->texture_offset));
+	      brw_imm_ud(inst->texture_offset));
       brw_pop_insn_state(p);
    } else if (inst->header_present) {
       /* Set up an implied move from g0 to the MRF. */
@@ -1040,6 +1043,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
+   case SHADER_OPCODE_TG4:
       generate_tex(inst, dst, src[0]);
       break;