diff options
| author | Rob Clark <[email protected]> | 2016-06-24 14:28:51 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2016-07-02 09:00:19 -0400 |
| commit | f78a6b1ce398a537d77c25b1a93f156109086975 (patch) | |
| tree | 0d891e0156328ae8462f1e7cad56b373e7ab8607 /src/mesa/drivers/dri/i965 | |
| parent | 202710d11057dfe4416770752cf5fd5b3f766999 (diff) | |
glsl: add driconf to zero-init unintialized vars
Some games are sloppy.. perhaps because it is defined behavior for DX or
perhaps because nv blob driver defaults things to zero.
So add driconf param to force uninitialized variables to default to zero.
This issue was observed with rust, from steam store. But has surfaced
elsewhere in the past.
Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 5e3c9d169b3..3f0c2e3b483 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -827,6 +827,8 @@ brw_process_driconf_options(struct brw_context *brw) ctx->Const.AllowGLSLExtensionDirectiveMidShader = driQueryOptionb(options, "allow_glsl_extension_directive_midshader"); + ctx->Const.GLSLZeroInit = driQueryOptionb(options, "glsl_zero_init"); + brw->dual_color_blend_by_location = driQueryOptionb(options, "dual_color_blend_by_location"); } diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 1c71e09e7ad..432ab7bdb63 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -88,6 +88,10 @@ DRI_CONF_BEGIN DRI_CONF_DESC(en, "Perform code generation at shader link time.") DRI_CONF_OPT_END DRI_CONF_SECTION_END + + DRI_CONF_SECTION_MISCELLANEOUS + DRI_CONF_GLSL_ZERO_INIT("false") + DRI_CONF_SECTION_END DRI_CONF_END }; |