diff options
| author | Chia-I Wu <[email protected]> | 2013-04-10 21:32:30 +0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2013-04-24 12:56:17 -0700 |
| commit | 9d0ad4c2f2eb89bab82194478180df570cc7aa4e (patch) | |
| tree | 5f960dd6a6153756e09f5dd796fb56d8ff88a943 /src/mesa/drivers/dri/i965 | |
| parent | 75d402b2118c55b0131025016a859a35733746b5 (diff) | |
i965/gen7: fix encoding of (huge) surface size for BRW_SURFACE_BUFFER
Unlike GEN6, the bits of entry count are distributed like this
width = (entry_count & 0x0000007f); /* bits [6:0] */
height = (entry_count & 0x001fff80) >> 7; /* bits [20:7] */
depth = (entry_count & 0x7fe00000) >> 21; /* bits [30:21] */
The maximum entry count is still limited to 2^27.
This was noted while going over the PRM. No test is impacted, because
1<<20 (the bit that moved) is much larger than GL_UNIFORM_BLOCK_MAX_SIZE,
GL_MAX_TEXTURE_BUFFER_SIZE, or MAX_*_UNIFORM_COMPONENTS.
v2: Explain more in the commit message (by anholt)
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 2c12be3c635..761ceb07d12 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -269,9 +269,11 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, int texel_size = _mesa_get_format_bytes(format); int w = intel_obj->Base.Size / texel_size; + + /* note that these differ from GEN6 */ surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */ - SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); /* 19:7 */ - surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | /* bits 26:20 */ + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */ + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */ (texel_size - 1); } @@ -403,9 +405,10 @@ gen7_create_constant_surface(struct brw_context *brw, assert(bo); surf[1] = bo->offset + offset; /* reloc */ + /* note that these differ from GEN6 */ surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | - SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); - surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | (stride - 1); if (intel->is_haswell) { @@ -446,9 +449,10 @@ gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset) surf[1] = brw->shader_time.bo->offset; /* reloc */ + /* note that these differ from GEN6 */ surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | - SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); - surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH); + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH); /* Unlike texture or renderbuffer surfaces, we only do untyped operations * on the shader_time surface, so there's no need to set HSW channel |