diff options
| author | Eric Anholt <[email protected]> | 2019-08-29 16:05:20 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2019-10-20 04:39:48 +0000 |
| commit | d8741ad251d65b7cf2aa019ed5d0713a264bc941 (patch) | |
| tree | 297dca9fb48f35e24510833fd643134704f1517b /src/mesa/drivers/dri/i965 | |
| parent | 4f384ddf5febb5005af3be0a2d51e244fb11a43b (diff) | |
mesa: Redefine the RG formats as array formats.
This is the layout used in the GL API, and maps directly to PIPE
formats with no endianness trickery. As with the LA change, this
fixes big-endian fetching from texbos. Also cleans up some endian
shenanigans in shader images.
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 6127ed8a490..b42bbf870b6 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -58,9 +58,9 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format) [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL, [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY, [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM, - [MESA_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM, + [MESA_FORMAT_RG_UNORM8] = ISL_FORMAT_R8G8_UNORM, [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM, - [MESA_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM, + [MESA_FORMAT_RG_UNORM16] = ISL_FORMAT_R16G16_UNORM, [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM, [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT, @@ -125,10 +125,10 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format) [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT, [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM, - [MESA_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM, + [MESA_FORMAT_RG_SNORM8] = ISL_FORMAT_R8G8_SNORM, [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM, [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM, - [MESA_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM, + [MESA_FORMAT_RG_SNORM16] = ISL_FORMAT_R16G16_SNORM, [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM, [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM, [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM, diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 5716c7f254c..d6fb3e8d97c 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -219,9 +219,9 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format) case MESA_FORMAT_ETC2_SIGNED_R11_EAC: return MESA_FORMAT_R_SNORM16; case MESA_FORMAT_ETC2_RG11_EAC: - return MESA_FORMAT_R16G16_UNORM; + return MESA_FORMAT_RG_UNORM16; case MESA_FORMAT_ETC2_SIGNED_RG11_EAC: - return MESA_FORMAT_R16G16_SNORM; + return MESA_FORMAT_RG_SNORM16; default: /* Non ETC1 / ETC2 format */ return format; |