i965: Fixed the CopyImageSubData for ETC2 on Gen < 8

For CopyImageSubData to copy the data during the 1st draw call, we need
to update the shadow tree right before the rendering.

v2:
  - Added assertion that the miptree doesn't need update at the time we
  update the texture surface. (Nanley Chery)

v3:
  - As we now update the tree before the rendering we don't need to copy
  the data during the unmap anymore. Removed the unnecessary update from
  the intel_miptree_unmap in intel_mipmap_tree.c (Nanley Chery)

v4:
  - Fixed unrelated empty line removal (Nanley Chery)
  - As now the intel_upate_etc_shadow of intel_mipmap_tree.c is only
  called inside its following function, we don't need to declare it at
  the top of the file anymore. (Nanley Chery)

Reviewed-by: Nanley Chery <[email protected]>

3 files changed, 6 insertions, 18 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 40bcf82ae8d..d07349419cc 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -559,6 +559,11 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
           tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
          intel_update_r8stencil(brw, tex_obj->mt);
       }
+
+      if (intel_miptree_has_etc_shadow(brw, tex_obj->mt) &&
+          tex_obj->mt->shadow_needs_update) {
+         intel_miptree_update_etc_shadow_levels(brw, tex_obj->mt);
+      }
    }
 
    /* Resolve color for each active shader image. */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c3d267721e1..19a46fcf243 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -582,7 +582,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
          mt = mt->shadow_mt;
          format = ISL_FORMAT_R8_UINT;
       } else if (intel_miptree_needs_fake_etc(brw, mt)) {
-         assert(mt->shadow_mt);
+         assert(mt->shadow_mt && !mt->shadow_needs_update);
          mt = mt->shadow_mt;
       }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 976a004ade0..7146fcb6582 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -57,11 +57,6 @@ static void *intel_miptree_map_raw(struct brw_context *brw,
                                    GLbitfield mode);
 
 static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
-static void intel_miptree_update_etc_shadow(struct brw_context *brw,
-                                            struct intel_mipmap_tree *mt,
-                                            unsigned int level,
-                                            unsigned int slice,
-                                            int level_w, int level_h);
 
 static bool
 intel_miptree_supports_mcs(struct brw_context *brw,
@@ -3779,7 +3774,6 @@ intel_miptree_unmap(struct brw_context *brw,
                     unsigned int slice)
 {
    struct intel_miptree_map *map = mt->level[level].slice[slice].map;
-   int level_w, level_h;
 
    assert(mt->surf.samples == 1);
 
@@ -3789,21 +3783,10 @@ intel_miptree_unmap(struct brw_context *brw,
    DBG("%s: mt %p (%s) level %d slice %d\n", __func__,
        mt, _mesa_get_format_name(mt->format), level, slice);
 
-   level_w = minify(mt->surf.phys_level0_sa.width,
-                    level - mt->first_level);
-   level_h = minify(mt->surf.phys_level0_sa.height,
-                    level - mt->first_level);
-
    if (map->unmap)
 	   map->unmap(brw, mt, map, level, slice);
 
    intel_miptree_release_map(mt, level, slice);
-
-   if (intel_miptree_has_etc_shadow(brw, mt) && mt->shadow_needs_update) {
-      mt->shadow_needs_update = false;
-      intel_miptree_update_etc_shadow(brw, mt, level, slice, level_w,
-                                      level_h);
-   }
 }
 
 enum isl_surf_dim