diff options
| author | Lionel Landwerlin <[email protected]> | 2018-07-17 15:05:28 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2018-07-18 11:29:16 +0100 |
| commit | 83427acc87730d2fab2eddffbb19fc9d85863407 (patch) | |
| tree | 2b1acbcd78163b3e10d67424902d0db4a93384ff /src/mesa/drivers/dri/i965 | |
| parent | 1376f2824fc300692f29adbbe6245dea1b06ebec (diff) | |
i965: batchbuffer: write correct canonical offset with softpin
Addresses in the command streams should be in canonical form (i.e
bit[63:48] == bit[47]). If the [bo->gtt_offset, bo->gtt_offset +
target_offset] range contains the address 0x800000000000, the current
code will fail that criteria.
v2: Fix missing include (Lionel)
Fixes: 1c9053d0765dc6 ("i965: Prepare batchbuffer module for softpin support.")
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index df999ffeb1d..65d2c64e319 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -32,6 +32,7 @@ #include "brw_defines.h" #include "brw_state.h" #include "common/gen_decoder.h" +#include "common/gen_gem.h" #include "util/hash_table.h" @@ -922,7 +923,7 @@ emit_reloc(struct intel_batchbuffer *batch, if (target->kflags & EXEC_OBJECT_PINNED) { brw_use_pinned_bo(batch, target, reloc_flags & RELOC_WRITE); - return target->gtt_offset + target_offset; + return gen_canonical_address(target->gtt_offset + target_offset); } unsigned int index = add_exec_bo(batch, target); |