diff options
| author | Chad Versace <[email protected]> | 2012-06-18 18:25:25 -0700 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2012-07-16 14:11:12 -0700 |
| commit | a5a34b153d494ad4374e7b2c8ea13b1073a887e2 (patch) | |
| tree | d2fd53dd8e1a34c04fd5493c3d4bdd67c8b38117 /src/mesa/drivers/dri/i965 | |
| parent | 8ec721264c7ae0f73a520362963b2691bf098b9b (diff) | |
intel: Enable GL_OES_compressed_ETC1_RGB8_texture
Enable it for all hardware.
No current hardware supports ETC1, so this patch implements it by
translating the ETC1 data to RGBX data during the call to
glCompressedTexImage2D(). For details, see the doxygen for
intel_mipmap_tree::wraps_etc1.
Passes the Piglit test spec/OES_compressed_ETC1_RGB8_texture/miptree and
the ETC1 test in the GLES2 conformance suite.
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ddf38e3dd35..82e44f9b83a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -551,6 +551,11 @@ brw_init_surface_formats(struct brw_context *brw) ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true; ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true; ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true; + + /* On hardware that lacks support for ETC1, we map ETC1 to RGBX + * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1. + */ + ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true; } bool |