diff options
| author | Kristian Høgsberg <[email protected]> | 2012-07-04 23:09:14 -0400 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2012-07-11 15:28:35 -0400 |
| commit | 02ebad900db4ef1ac42cbfb41b433919a4c857a2 (patch) | |
| tree | 581006f315275f6f7a9a6b7e1756b819e0d5100b /src/mesa/drivers/dri/i965 | |
| parent | 44a2b57f93ab68f873eab543f1ecb9dc7f230a7e (diff) | |
intel: Add offset field to miptree
This lets us specify an offset into the bo where the miptree starts,
which will let us set up a texture for a single plane in a planar buffer.
Signed-off-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 26e65afabd4..04ae6b23289 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -736,7 +736,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) sampler->sRGBDecode) << BRW_SURFACE_FORMAT_SHIFT)); - surf[1] = intelObj->mt->region->bo->offset; /* reloc */ + surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | (width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -754,7 +754,8 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + 4, - intelObj->mt->region->bo, 0, + intelObj->mt->region->bo, + intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index d34bf53d480..557f36f1be0 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -273,7 +273,8 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) * - render_cache_read_write (exists on gen6 but ignored here) */ - surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */ + surf->ss1.base_addr = + intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ surf->ss2.width = width - 1; surf->ss2.height = height - 1; @@ -303,7 +304,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + offsetof(struct gen7_surface_state, ss1), - intelObj->mt->region->bo, 0, + intelObj->mt->region->bo, intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); gen7_check_surface_setup(surf, false /* is_render_target */); |