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authorChad Versace <[email protected]>2011-05-23 13:47:57 -0700
committerChad Versace <[email protected]>2011-05-25 07:41:32 -0700
commita9e65097855468529242f9076bd6ef2a6c8062c1 (patch)
tree1e4c3ef3a0364b128960c5e63c886e466636c9c2 /src/mesa/drivers/dri/i965
parent1a1411e09b23fce9977f7926dba4f1f0c8f3c5ec (diff)
intel: Add is_hiz_depth_format() to intel_contex.vtbl
Given a format, is_hiz_depth_format() indicates if HiZ can be enabled on a depthbuffer of that format. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 9f99ef57214..69650e1df77 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -136,6 +136,16 @@ static void brw_invalidate_state( struct intel_context *intel, GLuint new_state
/* nothing */
}
+/**
+ * \see intel_context.vtbl.is_hiz_depth_format
+ */
+static bool brw_is_hiz_depth_format(struct intel_context *intel,
+ gl_format format)
+{
+ /* In the future, this will support Z_FLOAT32. */
+ return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
+}
+
void brwInitVtbl( struct brw_context *brw )
{
@@ -152,4 +162,5 @@ void brwInitVtbl( struct brw_context *brw )
brw->intel.vtbl.set_draw_region = brw_set_draw_region;
brw->intel.vtbl.debug_batch = brw_debug_batch;
brw->intel.vtbl.render_target_supported = brw_render_target_supported;
+ brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
}