diff options
author | Paul Berry <[email protected]> | 2012-07-09 11:10:52 -0700 |
---|---|---|
committer | Paul Berry <[email protected]> | 2012-07-20 09:35:37 -0700 |
commit | f91b4d92b97664e6354f66138705e93bec363ba0 (patch) | |
tree | addd886db17a102421be97267acb57efbfccaab6 /src/mesa/drivers/dri/i965 | |
parent | e5d983267a98bf9f73f0ea981eaca339b975a8db (diff) |
i965/blorp: Optimize manual_blend() for compressed multisampled surfaces.
When downsampling a compressed multisampled surface, we can take a
shortcut to downsample any pixels that were completely covered by a
single primitive. In this case, the first color value we fetch is the
correct final color for the downsampled pixel, so we can skip the rest
of the blending operation.
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 32fd48e2061..c8db662e23a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -1143,6 +1143,26 @@ brw_blorp_blit_program::manual_blend() } texel_fetch(texture_data[stack_depth++]); + if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) { + /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface) + * suggests an optimization: + * + * "A simple optimization with probable large return in + * performance is to compare the MCS value to zero (indicating + * all samples are on sample slice 0), and sample only from + * sample slice 0 using ld2dss if MCS is zero." + * + * Note that in the case where the MCS value is zero, sampling from + * sample slice 0 using ld2dss and sampling from sample 0 using + * ld2dms are equivalent (since all samples are on sample slice 0). + * Since we have already sampled from sample 0, all we need to do is + * skip the remaining fetches and averaging if MCS is zero. + */ + brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ, + mcs_data, brw_imm_ud(0)); + brw_IF(&func, BRW_EXECUTE_16); + } + /* Do count_trailing_one_bits(i) times */ for (int j = count_trailing_one_bits(i); j-- > 0; ) { assert(stack_depth >= 2); @@ -1169,6 +1189,9 @@ brw_blorp_blit_program::manual_blend() brw_imm_f(1.0/num_samples)); } } + + if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) + brw_ENDIF(&func); } /** |