diff options
author | Jason Ekstrand <[email protected]> | 2017-05-12 16:32:17 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2017-05-26 07:58:01 -0700 |
commit | 6d11362d8b0325ab1f9d12a93323d36ad92d24b0 (patch) | |
tree | c2282d72c5d80b8509fe7a112ee23e4019553d8c /src/mesa/drivers/dri/i965/intel_fbo.c | |
parent | fa13ef285df887d31f7012a4f32a4ff46a5920dc (diff) |
i965: Use blorp for color blits on gen4-5
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_fbo.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 66 |
1 files changed, 17 insertions, 49 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 21e8e86d2c1..60a6d0f4554 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -886,6 +886,22 @@ intel_blit_framebuffer(struct gl_context *ctx, if (!_mesa_check_conditional_render(ctx)) return; + if (brw->gen < 6) { + /* On gen4-5, try BLT first. + * + * Gen4-5 have a single ring for both 3D and BLT operations, so there's + * no inter-ring synchronization issues like on Gen6+. It is apparently + * faster than using the 3D pipeline. Original Gen4 also has to rebase + * and copy miptree slices in order to render to unaligned locations. + */ + mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb, + srcX0, srcY0, srcX1, srcY1, + dstX0, dstY0, dstX1, dstY1, + mask); + if (mask == 0x0) + return; + } + mask = brw_blorp_framebuffer(brw, readFb, drawFb, srcX0, srcY0, srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, @@ -919,51 +935,6 @@ intel_blit_framebuffer(struct gl_context *ctx, } /** - * Gen4-5 implementation of glBlitFrameBuffer(). - * - * Tries BLT, Meta, then swrast. - * - * Gen4-5 have a single ring for both 3D and BLT operations, so there's no - * inter-ring synchronization issues like on Gen6+. It is apparently faster - * than using the 3D pipeline. Original Gen4 also has to rebase and copy - * miptree slices in order to render to unaligned locations. - */ -static void -gen4_blit_framebuffer(struct gl_context *ctx, - struct gl_framebuffer *readFb, - struct gl_framebuffer *drawFb, - GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, - GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, - GLbitfield mask, GLenum filter) -{ - /* Page 679 of OpenGL 4.4 spec says: - * "Added BlitFramebuffer to commands affected by conditional rendering in - * section 10.10 (Bug 9562)." - */ - if (!_mesa_check_conditional_render(ctx)) - return; - - mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb, - srcX0, srcY0, srcX1, srcY1, - dstX0, dstY0, dstX1, dstY1, - mask); - if (mask == 0x0) - return; - - mask = _mesa_meta_BlitFramebuffer(ctx, readFb, drawFb, - srcX0, srcY0, srcX1, srcY1, - dstX0, dstY0, dstX1, dstY1, - mask, filter); - if (mask == 0x0) - return; - - _swrast_BlitFramebuffer(ctx, readFb, drawFb, - srcX0, srcY0, srcX1, srcY1, - dstX0, dstY0, dstX1, dstY1, - mask, filter); -} - -/** * Does the renderbuffer have hiz enabled? */ bool @@ -1110,10 +1081,7 @@ intel_fbo_init(struct brw_context *brw) dd->UnmapRenderbuffer = intel_unmap_renderbuffer; dd->RenderTexture = intel_render_texture; dd->ValidateFramebuffer = intel_validate_framebuffer; - if (brw->gen >= 6) - dd->BlitFramebuffer = intel_blit_framebuffer; - else - dd->BlitFramebuffer = gen4_blit_framebuffer; + dd->BlitFramebuffer = intel_blit_framebuffer; dd->EGLImageTargetRenderbufferStorage = intel_image_target_renderbuffer_storage; |