diff options
| author | Kenneth Graunke <[email protected]> | 2014-03-04 16:30:28 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-03-25 15:14:08 -0700 |
| commit | ee4484be3dc827cf15bcf109f5e680dbf1dfbf34 (patch) | |
| tree | 7109825c6c2314f893abca7efc7d06db8706140f /src/mesa/drivers/dri/i965/gen8_misc_state.c | |
| parent | 1afe3359258a9e89b62c8638761f52d78f6d1cbc (diff) | |
i965: Set Broadwell MOCS values everywhere it's possible.
This patch introduces two pre-canned MOCS values: BDW_MOCS_WB
(write-back, all caches) and BDW_MOCS_WT (write-through, all caches).
We use write-through caching for render targets, and write-back for
all other data. (At least on Haswell, I believe write-back LLC/eLLC
didn't work for scan-out buffers, while write-through did.)
No performance analysis has been done on the impact of this patch.
Signed-off-by: Kenneth Graunke <[email protected]>
Acked-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen8_misc_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_misc_state.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index 72ac2b23588..464138886ef 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -37,18 +37,21 @@ static void upload_state_base_address(struct brw_context *brw) OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2)); /* General state base address: stateless DP read/write requests */ OUT_BATCH(0); - OUT_BATCH(1); - OUT_BATCH(0); + OUT_BATCH(BDW_MOCS_WB << 2 | 1); + OUT_BATCH(BDW_MOCS_WB << 16); /* Surface state base address: */ - OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); + OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, + BDW_MOCS_WB << 4 | 1); /* Dynamic state base address: */ OUT_RELOC64(brw->batch.bo, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, + BDW_MOCS_WB << 4 | 1); /* Indirect object base address: MEDIA_OBJECT data */ OUT_BATCH(0); - OUT_BATCH(1); + OUT_BATCH(BDW_MOCS_WB << 4 | 1); /* Instruction base address: shader kernels (incl. SIP) */ - OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + BDW_MOCS_WB << 4 | 1); /* General state buffer size */ OUT_BATCH(0xfffff001); |