i965/gen7: Use the generic ISL-based path for renderbuffer surfaces

Signed-off-by: Jason Ekstrand <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Chad Versace <[email protected]>

1 files changed, 1 insertions, 193 deletions

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index bdb4f66d1e7..bb94f2d9578 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -39,79 +39,6 @@
 #include "brw_defines.h"
 #include "brw_wm.h"
 
-uint32_t
-gen7_surface_tiling_mode(uint32_t tiling)
-{
-   switch (tiling) {
-   case I915_TILING_X:
-      return GEN7_SURFACE_TILING_X;
-   case I915_TILING_Y:
-      return GEN7_SURFACE_TILING_Y;
-   default:
-      return GEN7_SURFACE_TILING_NONE;
-   }
-}
-
-
-uint32_t
-gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
-{
-   uint32_t ss4 = 0;
-
-   assert(num_samples <= 16);
-
-   /* The SURFACE_MULTISAMPLECOUNT_X enums are simply log2(num_samples) << 3. */
-   ss4 |= (ffs(MAX2(num_samples, 1)) - 1) << 3;
-
-   if (layout == INTEL_MSAA_LAYOUT_IMS)
-      ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
-   else
-      ss4 |= GEN7_SURFACE_MSFMT_MSS;
-
-   return ss4;
-}
-
-
-void
-gen7_set_surface_mcs_info(struct brw_context *brw,
-                          uint32_t *surf,
-                          uint32_t surf_offset,
-                          const struct intel_mipmap_tree *mcs_mt,
-                          bool is_render_target)
-{
-   /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
-    *
-    *     "The MCS surface must be stored as Tile Y."
-    */
-   assert(mcs_mt->tiling == I915_TILING_Y);
-
-   /* Compute the pitch in units of tiles.  To do this we need to divide the
-    * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
-    */
-   unsigned pitch_tiles = mcs_mt->pitch / 128;
-
-   /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
-    * GPU address of the MCS buffer; the lower 12 bits contain other control
-    * information.  Since buffer addresses are always on 4k boundaries (and
-    * thus have their lower 12 bits zero), we can use an ordinary reloc to do
-    * the necessary address translation.
-    */
-   assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
-
-   surf[6] = GEN7_SURFACE_MCS_ENABLE |
-             SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
-             mcs_mt->bo->offset64;
-
-   drm_intel_bo_emit_reloc(brw->batch.bo,
-                           surf_offset + 6 * 4,
-                           mcs_mt->bo,
-                           surf[6] & 0xfff,
-                           is_render_target ? I915_GEM_DOMAIN_RENDER
-                           : I915_GEM_DOMAIN_SAMPLER,
-                           is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
-}
-
-
 void
 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 {
@@ -291,130 +218,11 @@ gen7_emit_null_surface_state(struct brw_context *brw,
    gen7_check_surface_setup(surf, true /* is_render_target */);
 }
 
-/**
- * Sets up a surface state structure to point at the given region.
- * While it is only used for the front/back buffer currently, it should be
- * usable for further buffers when doing ARB_draw_buffer support.
- */
-static uint32_t
-gen7_update_renderbuffer_surface(struct brw_context *brw,
-                                 struct gl_renderbuffer *rb,
-                                 bool layered, unsigned unit /* unused */,
-                                 uint32_t surf_index)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   struct intel_mipmap_tree *mt = irb->mt;
-   uint32_t format;
-   /* _NEW_BUFFERS */
-   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
-   uint32_t surftype;
-   bool is_array = false;
-   int depth = MAX2(irb->layer_count, 1);
-   const uint8_t mocs = GEN7_MOCS_L3;
-   uint32_t offset;
-
-   int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
-
-   GLenum gl_target = rb->TexImage ?
-                         rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
-
-   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
-                                    &offset);
-   memset(surf, 0, 8 * 4);
-
-   intel_miptree_used_for_rendering(irb->mt);
-
-   /* Render targets can't use IMS layout */
-   assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-
-   assert(brw_render_target_supported(brw, rb));
-   format = brw->render_target_format[rb_format];
-   if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
-      _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                    __func__, _mesa_get_format_name(rb_format));
-   }
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-      surftype = BRW_SURFACE_2D;
-      is_array = true;
-      depth *= 6;
-      break;
-   case GL_TEXTURE_3D:
-      depth = MAX2(irb->mt->logical_depth0, 1);
-      /* fallthrough */
-   default:
-      surftype = translate_tex_target(gl_target);
-      is_array = _mesa_is_array_texture(gl_target);
-      break;
-   }
-
-   surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
-             format << BRW_SURFACE_FORMAT_SHIFT |
-             (irb->mt->array_layout == ALL_SLICES_AT_EACH_LOD ?
-                 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL) |
-             gen7_surface_tiling_mode(mt->tiling);
-
-   if (irb->mt->valign == 4)
-      surf[0] |= GEN7_SURFACE_VALIGN_4;
-   if (irb->mt->halign == 8)
-      surf[0] |= GEN7_SURFACE_HALIGN_8;
-
-   if (is_array) {
-      surf[0] |= GEN7_SURFACE_IS_ARRAY;
-   }
-
-   assert(mt->offset % mt->cpp == 0);
-   surf[1] = mt->bo->offset64 + mt->offset;
-
-   assert(brw->has_surface_tile_offset);
-
-   surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
-             (irb->mt_level - irb->mt->first_level);
-
-   surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
-   surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
-             (mt->pitch - 1);
-
-   surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
-             min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
-             (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
-
-   if (irb->mt->mcs_mt) {
-      gen7_set_surface_mcs_info(brw, surf, offset,
-                                irb->mt->mcs_mt, true /* is RT */);
-   }
-
-   surf[7] = irb->mt->fast_clear_color_value;
-
-   if (brw->is_haswell) {
-      surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
-                  SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
-                  SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
-                  SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
-   }
-
-   drm_intel_bo_emit_reloc(brw->batch.bo,
-                           offset + 4,
-                           mt->bo,
-                           surf[1] - mt->bo->offset64,
-                           I915_GEM_DOMAIN_RENDER,
-                           I915_GEM_DOMAIN_RENDER);
-
-   gen7_check_surface_setup(surf, true /* is_render_target */);
-
-   return offset;
-}
-
 void
 gen7_init_vtable_surface_functions(struct brw_context *brw)
 {
    brw->vtbl.update_texture_surface = brw_update_texture_surface;
-   brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
+   brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
    brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
    brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
 }