diff options
| author | Ville Syrjälä <[email protected]> | 2013-08-12 16:07:08 +0300 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2013-08-21 10:14:04 -0700 |
| commit | e6893b99adcd6d9fb1bd49067883f66cc5603fe7 (patch) | |
| tree | 911dcf8c97d0cfb929ac509216f5f4a6aa149c2c /src/mesa/drivers/dri/i965/gen7_wm_state.c | |
| parent | 22161983c38fe19b393e5b983f4945dc527ccb1b (diff) | |
i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at hand for testing.
v2: Don't check (brw->gen == 7) in gen7 functions. (chadv)
Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index ba7a53d8705..e88db78f449 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -141,8 +141,6 @@ upload_ps_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; - BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); @@ -152,7 +150,7 @@ upload_ps_state(struct brw_context *brw) /* Pointer to the WM constant buffer. Covered by the set of * state flags from gen6_upload_wm_push_constants. */ - OUT_BATCH(brw->wm.push_const_offset | mocs); + OUT_BATCH(brw->wm.push_const_offset | GEN7_MOCS_L3); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); |