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authorEric Anholt <[email protected]>2012-04-25 13:58:07 -0700
committerEric Anholt <[email protected]>2012-05-23 10:46:15 -0700
commit29362875f2613ad87abe7725ce3c56c36d16cf9b (patch)
treeb244e2081aaa2067cb1f99f0330d9e23137edf5c /src/mesa/drivers/dri/i965/gen7_wm_state.c
parent175ad8050e3337f7065306017ea4eb8eae599f6d (diff)
i965/gen6+: Add support for GL_ARB_blend_func_extended.
v2: Add support for gen6, and don't turn it on if blending is disabled. (fixes GPU hang), and note it in docs/GL3.txt Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 2a0462f3fc9..f46e3f26ceb 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -109,6 +109,7 @@ static void
upload_ps_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
uint32_t dw2, dw4, dw5;
const int max_threads_shift = brw->intel.is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
@@ -176,6 +177,17 @@ upload_ps_state(struct brw_context *brw)
if (brw->wm.prog_data->nr_params > 0)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
+ /* CACHE_NEW_WM_PROG | _NEW_COLOR
+ *
+ * The hardware wedges if you have this bit set but don't turn on any dual
+ * source blend factors.
+ */
+ if (brw->wm.prog_data->dual_src_blend &&
+ (ctx->Color.BlendEnabled & 1) &&
+ ctx->Color.Blend[0]._UsesDualSrc) {
+ dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
+ }
+
/* BRW_NEW_FRAGMENT_PROGRAM */
if (brw->fragment_program->Base.InputsRead != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
@@ -213,7 +225,8 @@ upload_ps_state(struct brw_context *brw)
const struct brw_tracked_state gen7_ps_state = {
.dirty = {
- .mesa = _NEW_PROGRAM_CONSTANTS,
+ .mesa = (_NEW_PROGRAM_CONSTANTS |
+ _NEW_COLOR),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_PS_BINDING_TABLE |
BRW_NEW_BATCH),