diff options
| author | Chad Versace <[email protected]> | 2013-07-18 10:04:17 -0700 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2013-07-18 16:18:22 -0700 |
| commit | 2273b652bb884a6188af7f8d063d0d0fc5497054 (patch) | |
| tree | d32ea20bfe8cb36dce82f3772ddb7b346efe982f /src/mesa/drivers/dri/i965/gen7_wm_state.c | |
| parent | 2f346395f5109c0fc4db86de3d2754001ddf0bb9 (diff) | |
i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS
Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
In blorp, change only the PS packet, because the VS packet is disabled.
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 8f9037136a6..1bc6e2ec231 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -141,6 +141,8 @@ upload_ps_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); @@ -150,7 +152,7 @@ upload_ps_state(struct brw_context *brw) /* Pointer to the WM constant buffer. Covered by the set of * state flags from gen6_upload_wm_push_constants. */ - OUT_BATCH(brw->wm.push_const_offset); + OUT_BATCH(brw->wm.push_const_offset | mocs); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); |