diff options
author | Paul Berry <[email protected]> | 2012-06-22 20:45:49 -0700 |
---|---|---|
committer | Paul Berry <[email protected]> | 2012-06-26 07:45:54 -0700 |
commit | 9ea60ce58f8494e0b79771f93227f4b8181731de (patch) | |
tree | 438216882f43955a524eb736732640a0b03f92bb /src/mesa/drivers/dri/i965/gen6_multisample_state.c | |
parent | 4bde1ba7fb6253e80197d3645b23893424ef756b (diff) |
i965/msaa: Implement glSampleCoverage.
This patch enables glSampleCoverage() functionality, which allows the
client program to specify that only a portion of the samples be lit up
when performing multisampled rendering. i965 supports
glSampleCoverage() through the 3DSTATE_SAMPLE_MASK command packet,
which allows the driver to specify a bitfield indicating which samples
to light up.
Fixes piglit tests "EXT_framebuffer_multisample/sample-coverage {2,4}
{inverted,non-inverted}".
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_multisample_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_multisample_state.c | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c index 3cf94f68bdb..f0648c3fcc7 100644 --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c @@ -56,7 +56,8 @@ gen6_emit_3dstate_multisample(struct brw_context *brw, */ void gen6_emit_3dstate_sample_mask(struct brw_context *brw, - unsigned num_samples) + unsigned num_samples, float coverage, + bool coverage_invert) { struct intel_context *intel = &brw->intel; @@ -65,7 +66,15 @@ gen6_emit_3dstate_sample_mask(struct brw_context *brw, BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2)); - OUT_BATCH(num_samples > 0 ? 15 : 1); + if (num_samples > 0) { + int coverage_int = (int) (num_samples * coverage + 0.5); + uint32_t coverage_bits = (1 << coverage_int) - 1; + if (coverage_invert) + coverage_bits ^= (1 << num_samples) - 1; + OUT_BATCH(coverage_bits); + } else { + OUT_BATCH(1); + } ADVANCE_BATCH(); } @@ -75,6 +84,14 @@ static void upload_multisample_state(struct brw_context *brw) struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; unsigned num_samples = 0; + float coverage = 1.0; + float coverage_invert = false; + + /* _NEW_MULTISAMPLE */ + if (ctx->Multisample._Enabled && ctx->Multisample.SampleCoverage) { + coverage = ctx->Multisample.SampleCoverageValue; + coverage_invert = ctx->Multisample.SampleCoverageInvert; + } /* _NEW_BUFFERS */ if (ctx->DrawBuffer->_ColorDrawBuffers[0]) @@ -84,13 +101,14 @@ static void upload_multisample_state(struct brw_context *brw) intel_emit_post_sync_nonzero_flush(intel); gen6_emit_3dstate_multisample(brw, num_samples); - gen6_emit_3dstate_sample_mask(brw, num_samples); + gen6_emit_3dstate_sample_mask(brw, num_samples, coverage, coverage_invert); } const struct brw_tracked_state gen6_multisample_state = { .dirty = { - .mesa = _NEW_BUFFERS, + .mesa = _NEW_BUFFERS | + _NEW_MULTISAMPLE, .brw = BRW_NEW_CONTEXT, .cache = 0 }, |