diff options
author | Paul Berry <[email protected]> | 2012-07-09 20:05:41 -0700 |
---|---|---|
committer | Paul Berry <[email protected]> | 2012-07-24 14:52:57 -0700 |
commit | 691c55f3560e5b8b9db9ecd2c089f13b41ec684f (patch) | |
tree | 70529f8ccb8ac44a81e5ce9c17d16a3fe3f32848 /src/mesa/drivers/dri/i965/gen6_multisample_state.c | |
parent | 48fdfbcb58929f1c20cb21190846faa388b1abba (diff) |
i965/msaa: Control multisampling behaviour via the visual.
Previously, we used the number of samples in draw buffer 0 to
determine whether to set up the 3D pipeline for multisampling. Using
the visual is cleaner, and has the benefit of working properly when
there is no color buffer.
Fixes all piglit tests "EXT_framebuffer_multisample/no-color" on Gen7.
On Gen6, the "depth-computed" variants of these tests still fail; this
will be addresed in a later patch.
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_multisample_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_multisample_state.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c index f0648c3fcc7..336e7c508a5 100644 --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c @@ -83,20 +83,18 @@ static void upload_multisample_state(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; - unsigned num_samples = 0; float coverage = 1.0; float coverage_invert = false; + /* _NEW_BUFFERS */ + unsigned num_samples = ctx->DrawBuffer->Visual.samples; + /* _NEW_MULTISAMPLE */ if (ctx->Multisample._Enabled && ctx->Multisample.SampleCoverage) { coverage = ctx->Multisample.SampleCoverageValue; coverage_invert = ctx->Multisample.SampleCoverageInvert; } - /* _NEW_BUFFERS */ - if (ctx->DrawBuffer->_ColorDrawBuffers[0]) - num_samples = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples; - /* 3DSTATE_MULTISAMPLE is nonpipelined. */ intel_emit_post_sync_nonzero_flush(intel); |