i965: Emit the depth/stencil state pointer directly, not via atoms.

See two commits ago for the rationale.  This allows us to delete the
whole gen7_cc_state.c file.

This does move these commands before the depth stall flushes from
brw_emit_depthbuffer, which may be a problem.  The documentation for
3DSTATE_DEPTH_BUFFER mentions that depth stall flushes are required
before changing any depth/stencil buffer state, but explicitly lists
3DSTATE_DEPTH_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER,
and 3DSTATE_CLEAR_PARAMS.  It does not mention this particular packet
(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS).

No observed Piglit regressions on Sandybridge or Ivybridge.

Together with the last two commits, this makes a cairo-gl benchmark
faster by 0.324552% +/- 0.258355% on Ivybridge.  No statistically
significant change on Sandybridge.  (Thanks to Eric for the numbers.)

Signed-off-by: Kenneth Graunke <[email protected]>

1 files changed, 0 insertions, 22 deletions

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index ef0f62d98bd..b4a570960c8 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -300,25 +300,3 @@ const struct brw_tracked_state gen6_color_calc_state = {
    },
    .emit = gen6_upload_color_calc_state,
 };
-
-static void upload_cc_state_pointers(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen6_cc_state_pointers = {
-   .dirty = {
-      .mesa = 0,
-      .brw = (BRW_NEW_BATCH |
-	      BRW_NEW_STATE_BASE_ADDRESS),
-      .cache = CACHE_NEW_DEPTH_STENCIL_STATE
-   },
-   .emit = upload_cc_state_pointers,
-};