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authorKenneth Graunke <[email protected]>2013-08-13 11:34:01 -0700
committerKenneth Graunke <[email protected]>2013-08-16 15:03:38 -0700
commit8fba8d4ee7632ae185f70356093e10a563ea64cd (patch)
treebd96dffc9daff543f5a45ebf251eeb4837e46607 /src/mesa/drivers/dri/i965/gen6_blorp.cpp
parent9c48ae751ab28f35eb878551d24c071be0ce11b0 (diff)
i965: Add Gen6 depth stall flushes before disabling depth in BLORP.
We emit these before configuring depth in the normal path, or actually using the depth buffer in BLORP - we just failed to emit them when disabling depth altogether. On Sandybridge, this also requires the post_sync_nonzero flush. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_blorp.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index a4a90817a8c..129c11361a6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -914,6 +914,9 @@ static void
gen6_blorp_emit_depth_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ intel_emit_post_sync_nonzero_flush(brw);
+ intel_emit_depth_stall_flushes(brw);
+
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |