diff options
| author | Eric Anholt <[email protected]> | 2013-02-04 14:21:24 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2013-05-28 12:40:21 -0700 |
| commit | 0ae294bf7c885aa587c7bde54fd4f9bf70af02d4 (patch) | |
| tree | a01f6aff066cc2e4c7726d87442022831ddd3052 /src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |
| parent | 4e8eafd8f44d763a7d079abea89388fb738bb723 (diff) | |
intel: Rename intel_renderbuffer_tile_offsets.
This makes it more consistent with intel_miptree_get_tile_offsets().
Reviewed-and-tested-by: Ian Romanick <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Acked-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 2022159617e..f73ea20442e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -1329,7 +1329,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); if (rb->TexImage && !brw->has_surface_tile_offset) { - intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); + intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); if (tile_x != 0 || tile_y != 0) { /* Original gen4 hardware couldn't draw to a non-tile-aligned @@ -1358,7 +1358,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, format << BRW_SURFACE_FORMAT_SHIFT); /* reloc */ - surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) + + surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + region->bo->offset); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | |