diff options
| author | Paul Berry <[email protected]> | 2013-09-03 12:15:53 -0700 |
|---|---|---|
| committer | Paul Berry <[email protected]> | 2013-09-16 12:53:46 -0700 |
| commit | 875972029eddfd53cb90a8e34e9f27b2afed119f (patch) | |
| tree | e02dabd0a298a6f875c126cc0b9a5026164efd47 /src/mesa/drivers/dri/i965/brw_wm.c | |
| parent | a4546ec114853235db375b20fb47ddcd6a7f21e7 (diff) | |
i965/fs: When >64 input components, order them to match prev pipeline stage.
Since the SF/SBE stage is only capable of performing arbitrary
reorderings of 16 varying slots, we can't arrange the fragment shader
inputs in an arbitrary order if there are more than 16 input varying
slots in use. We need to make sure that slots 16-31 match the
corresponding outputs of the previous pipeline stage.
The easiest way to accomplish this is to just make all varying slots
match up with the previous pipeline stage.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 1b23a4f5451..3d7ca2a4d03 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -466,7 +466,8 @@ static void brw_wm_populate_key( struct brw_context *brw, (ctx->Multisample.SampleAlphaToCoverage || ctx->Color.AlphaEnabled); /* BRW_NEW_VUE_MAP_GEOM_OUT */ - if (brw->gen < 6) + if (brw->gen < 6 || _mesa_bitcount_64(fp->program.Base.InputsRead & + BRW_FS_VARYING_INPUT_MASK) > 16) key->input_slots_valid = brw->vue_map_geom_out.slots_valid; /* The unique fragment program ID */ |