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authorTimothy Arceri <[email protected]>2016-10-05 16:24:56 +1100
committerTimothy Arceri <[email protected]>2016-10-06 16:04:03 +1100
commit7ef8286487562e1e8678ccc514e4054a682c0c89 (patch)
treefaea4e804b2ed47a6aba0aef20fbbbc29b39901f /src/mesa/drivers/dri/i965/brw_vs.c
parentb526a9b708b48c3d1c394783cba99f11eb17d0b9 (diff)
i965: get outputs written from nir info
This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vs.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index bd194ca226e..aa1ae285161 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -149,8 +149,9 @@ brw_codegen_vs_prog(struct brw_context *brw,
&prog_data.base.base);
}
- GLbitfield64 outputs_written =
- brw_vs_outputs_written(brw, key, vp->program.Base.OutputsWritten);
+ uint64_t outputs_written =
+ brw_vs_outputs_written(brw, key,
+ vp->program.Base.nir->info.outputs_written);
prog_data.inputs_read = vp->program.Base.InputsRead;
if (key->copy_edgeflag) {
@@ -339,8 +340,9 @@ brw_vs_populate_key(struct brw_context *brw,
}
}
- if (prog->OutputsWritten & (VARYING_BIT_COL0 | VARYING_BIT_COL1 |
- VARYING_BIT_BFC0 | VARYING_BIT_BFC1)) {
+ if (prog->nir->info.outputs_written &
+ (VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
+ VARYING_BIT_BFC1)) {
/* _NEW_LIGHT | _NEW_BUFFERS */
key->clamp_vertex_color = ctx->Light._ClampVertexColor;
}
@@ -399,8 +401,9 @@ brw_vs_precompile(struct gl_context *ctx,
brw_setup_tex_for_precompile(brw, &key.tex, prog);
key.program_string_id = bvp->id;
key.clamp_vertex_color =
- (prog->OutputsWritten & (VARYING_BIT_COL0 | VARYING_BIT_COL1 |
- VARYING_BIT_BFC0 | VARYING_BIT_BFC1));
+ (prog->nir->info.outputs_written &
+ (VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
+ VARYING_BIT_BFC1));
success = brw_codegen_vs_prog(brw, shader_prog, bvp, &key);