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authorKenneth Graunke <[email protected]>2014-01-18 14:32:49 -0800
committerKenneth Graunke <[email protected]>2014-01-22 17:18:53 -0800
commit15fc919491ea27bd395988a332502bdb23ee44d0 (patch)
tree6043b0540c85b4e5532a17c8893e7ec923f55d9e /src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
parentd58e03fe4f04c24c70c76e7ad86fd04b9130a711 (diff)
i965/vec4: Support arbitrarily large sampler state indices on Haswell+.
Like the scalar backend, we add an offset to the "Sampler State Pointer" field to select a group of 16 samplers, then use the "Sampler Index" field to select within that group. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index daf46b6ab82..8c287c244b5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2370,9 +2370,15 @@ vec4_visitor::visit(ir_texture *ir)
if (ir->op == ir_tg4)
inst->texture_offset |= gather_channel(ir, sampler) << 16;
- /* Texel offsets go in the message header; Gen4 also requires headers. */
+ /* The message header is necessary for:
+ * - Gen4 (always)
+ * - Texel offsets
+ * - Gather channel selection
+ * - Sampler indices too large to fit in a 4-bit value.
+ */
inst->header_present =
- brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4;
+ brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4 ||
+ sampler >= 16;
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->sampler = sampler;