aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
diff options
context:
space:
mode:
authorMatt Turner <[email protected]>2014-11-12 11:28:02 -0800
committerMatt Turner <[email protected]>2014-11-21 10:26:38 -0800
commitbd502139290ea902cbc4b5f535c102f8f98774b1 (patch)
tree60e9060bdca0add890fa5fba9b25cbb43971a48e /src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
parent645b471d619b654d3bacfa8598f759833e08db4e (diff)
i965: Combine offset/texture_offset fields.
texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_generator.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index e5225673812..0776a917456 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -319,7 +319,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
* use an implied move from g0 to the first message register.
*/
if (inst->header_present) {
- if (brw->gen < 6 && !inst->texture_offset) {
+ if (brw->gen < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = brw_vec8_grf(0, 0);
} else {
@@ -333,10 +333,10 @@ vec4_generator::generate_tex(vec4_instruction *inst,
brw_set_default_access_mode(p, BRW_ALIGN_1);
- if (inst->texture_offset) {
+ if (inst->offset) {
/* Set the texel offset bits in DWord 2. */
brw_MOV(p, get_element_ud(header, 2),
- brw_imm_ud(inst->texture_offset));
+ brw_imm_ud(inst->offset));
}
brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);