i965/vs: Implement register spilling.

To validate this code, I ran piglit -t vs quick.tests with the "go spill
everything" debugging code enabled.  There was only one regression:
glsl-vs-unroll-explosion simply ran out of registers.  This should be
fine in the real world, since no one actually spills every single
register.

NOTE: This is a candidate for the 9.0 branch. Even if it proves to have
bugs, it's likely better than simply failing to compile.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

1 files changed, 14 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 27758abeb53..22671f3f6ce 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -809,6 +809,20 @@ vec4_visitor::run()
       return false;
 
    setup_payload();
+
+   if (false) {
+      /* Debug of register spilling: Go spill everything. */
+      const int grf_count = virtual_grf_count;
+      float spill_costs[virtual_grf_count];
+      bool no_spill[virtual_grf_count];
+      evaluate_spill_costs(spill_costs, no_spill);
+      for (int i = 0; i < grf_count; i++) {
+         if (no_spill[i])
+            continue;
+         spill_reg(i);
+      }
+   }
+
    reg_allocate();
 
    if (failed)