diff options
| author | Eric Anholt <[email protected]> | 2013-02-05 16:21:07 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2013-02-13 18:10:20 -0800 |
| commit | 516d8be502885f5aadcc43aafe764e617f2593f4 (patch) | |
| tree | 68d997dacd5c5f4593c809a3f5fbbc1561f4f60e /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | |
| parent | bf91f0b03942d966cf453201dc52c4aa4049f8fa (diff) | |
i965: Remove writemask support from brw_SAMPLE().
The code was rather broken for non-XYZW on 8-wide, but all of our
callers were using XYZW anyway. For my experiments with using writemask
on texturing, I've been using manual header setup in the compiler
backends, since we want to actually know what registers are written for
optimization and register allocation.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_emit.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index 863ff7ce02b..cc2f5d4c8b0 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -372,7 +372,6 @@ vec4_generator::generate_tex(vec4_instruction *inst, src, SURF_INDEX_VS_TEXTURE(inst->sampler), inst->sampler, - WRITEMASK_XYZW, msg_type, 1, /* response length */ inst->mlen, |